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----------------------------------------------------------------------
----                                                              ----
---- PlTbUtils Fuctions and Procedures Package                    ----
----                                                              ----
---- This file is part of the PlTbUtils project                   ----
---- http://opencores.org/project,pltbutils                       ----
----                                                              ----
---- Description:                                                 ----
---- PlTbUtils is a collection of functions, procedures and       ----
---- components for easily creating stimuli and checking response ----
---- in automatic self-checking testbenches.                      ----
----                                                              ----
---- This file defines fuctions and procedures for controlling    ----
---- stimuli to a DUT and checking response.                      ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Per Larsson, pela@opencores.org                            ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use std.env.all; -- VHDL-2008
use work.txt_util.all;
use work.pltbutils_type_pkg.all; -- Use for VHDL-2002, comment out for VHDL-93
 
package pltbutils_func_pkg is
 
  -- See the package body for a description of the functions and procedures.
  constant C_PLTBUTILS_STRLEN  : natural := 80;
  constant C_PLTBUTILS_TIMEOUT : time    := 10 sec;
  constant C_WAIT_BEFORE_STOP_TIME : time := 1 us;
 
  -- Counters for number of checks and number of errors
  -- VHDL-2002:
  shared variable v_pltbutils_test_num  : pltbutils_p_integer_t;
  shared variable v_pltbutils_test_name : pltbutils_p_string_t;
  shared variable v_pltbutils_info      : pltbutils_p_string_t;
  shared variable v_pltbutils_chk_cnt   : pltbutils_p_integer_t;
  shared variable v_pltbutils_err_cnt   : pltbutils_p_integer_t;
  shared variable v_pltbutils_stop_sim  : pltbutils_p_std_logic_t;
  -- VHDL-1993:
  --shared variable v_pltbutils_test_num  : natural := 0;
  --shared variable v_pltbutils_test_name : string(1 to C_PLTBUTILS_STRLEN) := (others => ' ');
  --shared variable v_pltbutils_info      : string(1 to C_PLTBUTILS_STRLEN) := (others => ' ');
  --shared variable v_pltbutils_chk_cnt   : natural := 0;
  --shared variable v_pltbutils_err_cnt   : natural := 0;
  --shared variable v_pltbutils_stop_sim  : std_logic := '0';
 
  -- Global status- and control signal
  type pltbutils_sc_t is
    record
      test_num  : natural;
      test_name : string(1 to C_PLTBUTILS_STRLEN);
      info      : string(1 to C_PLTBUTILS_STRLEN);
      chk_cnt   : natural;
      err_cnt   : natural;
      stop_sim  : std_logic;
    end record;
  signal pltbutils_sc : pltbutils_sc_t;
 
  -- startsim 
  procedure startsim(
    constant testcase_name      : in    string;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
 
  -- endsim
  procedure endsim(
    signal   pltbutils_sc        : out pltbutils_sc_t;
    constant show_success_fail   : in   boolean := false;
    constant force               : in boolean := false
  );
 
  -- testname
  procedure testname(
    constant num                : in    integer := -1;
    constant name               : in    string;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure testname(
    constant name               : in    string;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
 
  -- print, printv, print2
  procedure print(
    constant active             : in    boolean;
    signal   s                  : out   string;
    constant txt                : in    string
  );
  procedure print(
    signal   s                  : out   string;
    constant txt                : in    string
  );
  procedure printv(
    constant active             : in    boolean;
    variable s                  : out   string;
    constant txt                : in    string
  );
  procedure printv(
    variable s                  : out   string;
    constant txt                : in    string
  );
  procedure printv(
    constant active             : in    boolean;
    variable s                  : inout pltbutils_p_string_t;
    constant txt                : in    string
  );
  procedure printv(
    variable s                  : inout pltbutils_p_string_t;
    constant txt                : in    string
  );
  procedure print(
    constant active             : in    boolean;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  );
  procedure print(
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  );
  procedure print2(
    constant active             : in    boolean;
    signal   s                  : out   string;
    constant txt                : in    string
  );
  procedure print2(
    signal   s                  : out   string;
    constant txt                : in    string
  );
  procedure print2(
    constant active             : in    boolean;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  );
  procedure print2(
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  );
 
  -- waitclks
  procedure waitclks(
    constant N                  : in    natural;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
 
  -- waitsig
  procedure waitsig(
    signal   s                  : in    integer;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    std_logic;
    constant value              : in    std_logic;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    std_logic;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    std_logic_vector;
    constant value              : in    std_logic_vector;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    std_logic_vector;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    unsigned;
    constant value              : in    unsigned;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    unsigned;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    signed;
    constant value              : in    signed;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
  procedure waitsig(
    signal   s                  : in    signed;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  );
 
  -- check
  procedure check(
    constant rpt                : in    string;
    constant data               : in    integer;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic;
    constant expected           : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    std_logic_vector;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    std_logic_vector;
    constant mask               : in    std_logic_vector;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    integer;
    constant mask               : in    std_logic_vector;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    unsigned;
    constant expected           : in    unsigned;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    unsigned;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    signed;
    constant expected           : in    signed;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant data               : in    signed;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
  procedure check(
    constant rpt                : in    string;
    constant expr               : in    boolean;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  );
 
  -- to_ascending
  function to_ascending(
    constant s                  : std_logic_vector
  ) return std_logic_vector;
  function to_ascending(
    constant s                  : unsigned
  ) return unsigned;
  function to_ascending(
    constant s                  : signed
  ) return signed;
 
  -- to_descending
  function to_descending(
    constant s                  : std_logic_vector
  ) return std_logic_vector;
  function to_descending(
    constant s                  : unsigned
  ) return unsigned;
  function to_descending(
    constant s                  : signed
  ) return signed;
 
  -- hxstr
  function hxstr(
    constant s                  : std_logic_vector;
    constant prefix             : string := ""
  ) return string;
  function hxstr(
    constant s                  : unsigned;
    constant prefix             : string := ""
  ) return string;
  function hxstr(
    constant s                  : signed;
    constant prefix             : string := ""
  ) return string;
 
  -- pltbutils internal procedure(s), do not call from user's code
  procedure pltbutils_sc_update(
    signal pltbutils_sc : out pltbutils_sc_t
  );
 
end package pltbutils_func_pkg;
 
package body pltbutils_func_pkg is
 
  ----------------------------------------------------------------------------
  -- startsim
  --
  -- procedure startsim(
  --   constant testcase_name      : in    string;
  --   signal   pltbutils_sc       : out   pltbutils_sc_t
  -- )
  --
  -- Displays a message at start of simulation message, and initializes
  -- PlTbUtils' global status and control signal.
  -- Call startsim() only once.
  --
  -- Arguments:
  --   testcase_name            Name of the test case, e.g. "tc1".
  --
  --   pltbutils_sc             PlTbUtils' global status- and control signal.
  --                            Must be set to pltbutils_sc.
  --
  -- NOTE:
  -- The start-of-simulation message is not only intended to be informative
  -- for humans. It is also intended to be searched for by scripts,
  -- e.g. for collecting results from a large number of regression tests.
  -- For this reason, the message must be consistent and unique.
  --
  -- DO NOT MODIFY the message "--- START OF SIMULATION ---".
  -- DO NOT OUTPUT AN IDENTICAL MESSAGE anywhere else.
  --
  -- Example:
  -- startsim("tc1", pltbutils_sc);
  ----------------------------------------------------------------------------
  procedure startsim(
    constant testcase_name      : in    string;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
    variable dummy : integer;
  begin
    printv(v_pltbutils_info, testcase_name);
    print(lf & "--- START OF SIMULATION ---");
    print("Testcase: " & testcase_name);
    print(time'image(now));
    -- VHDL-2002:
    v_pltbutils_stop_sim.clr;
    v_pltbutils_test_num.clr;
    v_pltbutils_test_name.set("START OF SIMULATION");
    v_pltbutils_chk_cnt.clr;
    v_pltbutils_err_cnt.clr;
    pltbutils_sc_update(pltbutils_sc);
    -- VHDL-1993:
    --v_pltbutils_stop_sim := '0';
    --v_pltbutils_test_num := 0;
    --printv(v_pltbutils_test_name, "START OF SIMULATION");
    --v_pltbutils_chk_cnt := 0;
    --v_pltbutils_err_cnt := 0;
    --pltbutils_sc_update(pltbutils_sc);
  end procedure startsim;
 
  ----------------------------------------------------------------------------
  -- endsim
  --
  -- procedure endsim(
  --   signal   pltbutils_sc       : out pltbutils_sc_t;
  --   constant show_success_fail  : in  boolean := false;
  --   constant force              : in  boolean := false
  -- )
  --
  -- Displays a message at end of simulation message, presents the simulation
  -- results, and stops the simulation. 
  -- Call endsim() it only once.
  --
  -- Arguments: 
  --   pltbutils_sc             PlTbUtils' global status- and control signal.
  --                            Must be set to pltbutils_sc.
  --
  --   show_success_fail        If true, endsim() shows "*** SUCCESS ***", 
  --                            "*** FAIL ***", or "*** NO CHECKS ***".
  --                            Optional, default is false.
  --
  --   force                    If true, forces the simulation to stop using an
  --                            assert failure statement. Use this option only
  --                            if the normal way of stopping the simulation
  --                            doesn't work (see below).
  --                            Optional, default is false.
  --
  -- The testbench should be designed so that all clocks stop when endsim()
  -- sets the signal stop_sim to '1'. This should stop the simulator.
  -- In some cases, that doesn't work, then set the force argument to true, which
  -- causes a false assert failure, which should stop the simulator.
  -- Scripts searching transcript logs for errors and failures, should ignore
  -- the failure with "--- FORCE END OF SIMULATION ---" as part of the report.
  --
  -- NOTE:
  -- The end-of-simulation messages and success/fail messages are not only
  -- intended to be informative for humans. They are also intended to be
  -- searched for by scripts, e.g. for collecting results from a large number
  -- of regression tests.
  -- For this reason, the message must be consistent and unique.
  --
  -- DO NOT MODIFY the messages "--- END OF SIMULATION ---", 
  -- "*** SUCCESS ***", "*** FAIL ***", "*** NO CHECKS ***".
  -- DO NOT OUTPUT IDENTICAL MESSAGES anywhere else.
  --
  -- Examples:
  -- endsim(pltbutils_sc);
  -- endsim(pltbutils_sc, true);
  -- endsim(pltbutils_sc, true, true);
  ----------------------------------------------------------------------------
  procedure endsim(
    signal   pltbutils_sc       : out pltbutils_sc_t;
    constant show_success_fail  : in  boolean := false;
    constant force              : in  boolean := false
  ) is
    variable l : line;
  begin
    printv(v_pltbutils_info, "");
    print(lf & "--- END OF SIMULATION ---");
    print("Note: the results presented below are based on the PlTbUtil's check() procedure calls.");
    print("      The design may contain more errors, for which there are no check() calls.");
    write(l, now, right, 14);
    writeline(output, l);
    write(l, v_pltbutils_chk_cnt.value, right, 11); -- VHDL-2002
    --write(l, v_pltbutils_chk_cnt, right, 11); -- VHDL-1993
    write(l, string'(" Checks"));
    writeline(output, l);
    write(l, v_pltbutils_err_cnt.value, right, 11); -- VHDL-2002
    --write(l, v_pltbutils_chk_cnt, right, 11); -- VHDL-1993
    write(l, string'(" Errors"));
    writeline(output, l);
 
    if show_success_fail then
       if v_pltbutils_err_cnt.value = 0 and v_pltbutils_chk_cnt.value > 0 then -- VHDL-2002
       --if v_pltbutils_err_cnt = 0 and v_pltbutils_chk_cnt > 0 then -- VHDL-1993
        print("*** SUCCESS ***");
      elsif v_pltbutils_chk_cnt.value > 0 then -- VHDL-2002
      --elsif v_pltbutils_chk_cnt > 0 then -- VHDL-1993
        print("*** FAIL ***");
      else
        print("*** NO CHECKS ***");
      end if;
    end if;
    -- VHDL-2002:
    v_pltbutils_stop_sim.set('1');
    v_pltbutils_test_num.clr;
    v_pltbutils_test_name.set("END OF SIMULATION");
    -- VHDL-1993:
    --v_pltbutils_stop_sim := '1';
    --v_pltbutils_test_num := 0;
    --printv(v_pltbutils_test_name, "END OF SIMULATION");
    pltbutils_sc_update(pltbutils_sc);
    wait for C_WAIT_BEFORE_STOP_TIME;
    stop(0); -- VHDL-2008
    assert not force
    report "--- FORCE END OF SIMULATION ---" &
           " (ignore this false failure message, it's not a real failure)"
    severity failure;
    wait;
  end procedure endsim;
 
  ----------------------------------------------------------------------------
  -- testname
  --
  -- procedure testname(
  --   constant num                : in    integer := -1;
  --   constant name               : in    string;
  --   signal   pltbutils_sc       : out   pltbutils_sc_t
  -- ) 
  --
  -- Sets a number (optional) and a name for a test. The number and name will
  -- be printed to the screen, and displayed in the simulator's waveform
  -- window. 
  -- The test number and name is also included if there errors reported by the
  -- check() procedure calls.
  --
  -- Arguments: 
  --   num                      Test number. Optional, default is to increment
  --                            the current test number.
  --
  --   name                     Test name.
  --
  --   pltbutils_sc             PlTbUtils' global status- and control signal.
  --                            Must be set to pltbutils_sc.
  --
  -- If the test number is omitted, a new test number is automatically
  -- computed by incrementing the current test number. 
  -- Manually setting the test number may make it easier to find the test code
  -- in the testbench code, though.
  --
  -- Examples:
  -- testname("Reset test", pltbutils_sc);
  -- testname(1, "Reset test", pltbutils_sc);
  ----------------------------------------------------------------------------
  procedure testname(
    constant num                : in    integer := -1;
    constant name               : in    string;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    -- VHDL-2002:
    if num = -1 then
      v_pltbutils_test_num.inc;
    else
      v_pltbutils_test_num.set(num);
    end if;
    v_pltbutils_test_name.set(name);
    pltbutils_sc_update(pltbutils_sc);
    print(lf & "Test " & str(v_pltbutils_test_num.value) & ": " & name);
    -- VHDL-1993:
    --if num = -1 then
    --  b_pltbutils_test_num := v_pltbutils_test_num + 1;
    --else
    --  v_pltbutils_test_num  := num;
    --end if;
    --printv(v_pltbutils_test_name, name);
    --pltbutils_sc_update(pltbutils_sc);
    --print("Test " & str(v_pltbutils_test_num) & ": " & name);
  end procedure testname;
 
  procedure testname(
    constant name               : in    string;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    testname(-1, name, pltbutils_sc);
  end procedure testname;
 
  ----------------------------------------------------------------------------
  -- print printv print2
  --
  -- procedure print(   
  --   signal   s                  : out   string;
  --   constant txt                : in    string
  -- ) 
  --
  -- procedure print(   
  --   constant active             : in    boolean;
  --   signal   s                  : out   string;
  --   constant txt                : in    string
  -- ) 
  --
  -- procedure print(
  --   signal   pltbutils_sc       : out   pltbutils_sc_t;
  --   constant txt                : in    string
  -- )
  --
  -- procedure print(
  --   constant active             : in    boolean;
  --   signal   pltbutils_sc       : out   pltbutils_sc_t;
  --   constant txt                : in    string
  -- )
  --
  -- procedure printv(
  --   variable s                  : out   string;
  --   constant txt                : in    string
  -- )
  --
  -- procedure printv(
  --   constant active             : in    boolean;
  --   variable s                  : out   string;
  --   constant txt                : in    string
  -- )
  --
  -- procedure print2(    
  --   signal   s                  : out   string;
  --   constant txt                : in    string
  -- )
  --
  -- procedure print2(    
  --   constant active             : in    boolean;
  --   signal   s                  : out   string;
  --   constant txt                : in    string
  -- )
  --
  -- procedure print2(    
  --   signal   pltbutils          : out   pltbutils_sc_t;
  --   constant txt                : in    string
  -- )
  --
  -- procedure print2(    
  --   constant active             : in    boolean;
  --   signal   pltbutils          : out   pltbutils_sc_t;
  --   constant txt                : in    string
  -- )
  --
  -- print() prints text messages to a signal for viewing in the simulator's
  -- waveform window. printv() does the same thing, but to a variable instead.
  -- print2() prints both to a signal and to the transcript window. 
  -- The type of the output can be string or pltbutils_sc_t.
  -- If the type is pltbutils_sc_t, the name can be no other than pltbutils_sc.
  --
  -- Arguments: 
  --   s                        Signal or variable of type string to be 
  --                            printed to.
  --
  --   txt                      The text.
  --
  --   active                   The text is only printed if active is true.
  --                            Useful for debug switches, etc.
  --
  --   pltbutils_sc             PlTbUtils' global status- and control signal 
  --                            of type pltbutils_sc_t. 
  --                            The name must be no other than pltbutils_sc.
  --
  -- If the string txt  is longer than the signal s, the text will be truncated.
  -- If txt  is shorter, s will be padded with spaces.
  --
  -- Examples:
  -- print(msg, "Hello, world"); -- Prints to signal msg
  -- print(G_DEBUG, msg, "Hello, world"); -- Prints to signal msg if 
  --                                      -- generic G_DEBUG is true
  -- printv(v_msg, "Hello, world"); -- Prints to variable msg
  -- print(pltbutils_sc, "Hello, world"); -- Prints to "info" in waveform window
  -- print2(msg, "Hello, world"); -- Prints to signal and transcript window 
  -- print(pltbutils_sc, "Hello, world"); -- Prints to "info" in waveform and
  --                                      -- transcript windows
  ----------------------------------------------------------------------------
  procedure print(
    constant active             : in    boolean;
    signal   s                  : out   string;
    constant txt                : in    string
  ) is
    variable j : positive := txt 'low;
  begin
    if active then
      for i in s'range loop
        if j <= txt 'high then
          s(i) <= txt (j);
        else
          s(i) <= ' ';
        end if;
        j := j + 1;
      end loop;
    end if;
  end procedure print;
 
  procedure print(
    signal   s                  : out   string;
    constant txt                : in    string
  ) is
  begin
    print(true, s, txt);
  end procedure print;
 
  procedure printv(
    constant active             : in    boolean;
    variable s                  : out   string;
    constant txt                : in    string
  ) is
    variable j : positive := txt 'low;
  begin
    if active then
      for i in s'range loop
        if j <= txt 'high then
          s(i) := txt (j);
        else
          s(i) := ' ';
        end if;
        j := j + 1;
      end loop;
    end if;
  end procedure printv;
 
  procedure printv(
    variable s                  : out   string;
    constant txt                : in    string
  ) is
  begin
    printv(true, s, txt);
  end procedure printv;
 
  -- VHDL-2002:
  procedure printv(
    constant active             : in    boolean;
    variable s                  : inout pltbutils_p_string_t;
    constant txt                : in    string
  ) is
    variable j : positive := txt 'low;
  begin
    if active then
      s.set(txt);
    end if;
  end procedure printv;
 
  procedure printv(
    variable s                  : inout pltbutils_p_string_t;
    constant txt                : in    string
  ) is
  begin
    printv(true, s, txt);
  end procedure printv;
 
  -- Print to info element in pltbutils_sc, which shows up in waveform window
  procedure print(
    constant active             : in    boolean;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  ) is
    variable j : positive := txt 'low;
  begin
    if active then
      printv(v_pltbutils_info, txt );
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure print;
 
  procedure print(
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  ) is
  begin
    print(true, pltbutils_sc, txt);
  end procedure print;
 
  procedure print2(
    constant active             : in    boolean;
    signal   s                  : out   string;
    constant txt                : in    string
  ) is
  begin
    if active then
      print(s, txt );
      print(txt);
    end if;
  end procedure print2;
 
  procedure print2(
    signal   s                  : out   string;
    constant txt                : in    string
  ) is
  begin
    print(true, s, txt);
  end procedure print2;
 
  procedure print2(
    constant active             : in    boolean;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  ) is
  begin
    print(pltbutils_sc, txt );
    print(txt);
  end procedure print2;
 
  procedure print2(
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant txt                : in    string
  ) is
  begin
    print(true, pltbutils_sc, txt);
  end procedure print2;
 
  ----------------------------------------------------------------------------
  -- waitclks
  --
  -- procedure waitclks(
  --   constant n                  : in    natural;
  --   signal   clk                : in    std_logic;
  --   signal   pltbutils_sc       : out   pltbutils_sc_t;
  --   constant falling            : in    boolean := false;
  --   constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  -- )
  --
  -- Waits specified amount of clock cycles of the specified clock.
  -- Or, to be more precise, a specified number of specified clock edges of
  -- the specified clock.
  --
  -- Arguments: 
  --   n                        Number of rising or falling clock edges to wait.
  --
  --   clk                      The clock to wait for.
  --
  --   pltbutils_sc             PlTbUtils' global status- and control signal.
  --                            Must be set to pltbutils_sc.
  --
  --   falling                  If true, waits for falling edges, otherwise
  --                            rising edges. Optional, default is false.
  --
  --   timeout                  Timeout time, in case the clock is not working.
  --                            Optional, default is C_PLTBUTILS_TIMEOUT.  
  --
  -- Examples:
  -- waitclks(5, sys_clk, pltbutils_sc);
  -- waitclks(5, sys_clk, pltbutils_sc, true);
  -- waitclks(5, sys_clk, pltbutils_sc, true, 1 ms);
  ----------------------------------------------------------------------------
  procedure waitclks(
    constant n                  : in    natural;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable i                  : natural := n;
    variable v_timeout_time     : time;
  begin
    v_timeout_time := now + timeout;
    while i > 0 loop
      if falling then
        wait until falling_edge(clk) for timeout / n;
      else
        wait until rising_edge(clk)  for timeout / n;
      end if;
      i := i - 1;
    end loop;
    if now >= v_timeout_time then
      assert false
      report "waitclks() timeout"
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitclks;
 
  ----------------------------------------------------------------------------
  -- waitsig
  --
  -- procedure waitsig(
  --   signal   s                  : in    integer|std_logic|std_logic_vector|unsigned|signed;
  --   constant value              : in    integer|std_logic|std_logic_vector|unsigned|signed;
  --   signal   clk                : in    std_logic;
  --   signal   pltbutils_sc       : out   pltbutils_sc_t;
  --   constant falling            : in    boolean := false;
  --   constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  -- )
  --
  -- Waits until a signal has reached a specified value after specified clock
  -- edge.
  --
  -- Arguments: 
  --   s                        The signal to test.
  --                            Supported types: integer, std_logic, 
  --                            std_logic_vector, unsigned, signed.
  --
  --   value                    Value to wait for.
  --                            Same type as data or integer.
  --
  --   clk                      The clock.
  --
  --   pltbutils_sc             PlTbUtils' global status- and control signal.
  --                            Must be set to pltbutils_sc.
  --
  --   falling                  If true, waits for falling edges, otherwise
  --                            rising edges. Optional, default is false.
  --
  --   timeout                  Timeout time, in case the clock is not working.
  --                            Optional, default is C_PLTBUTILS_TIMEOUT.  
  --
  -- Examples:
  -- waitsig(wr_en, '1', sys_clk, pltbutils_sc);
  -- waitsig(rd_en,   1, sys_clk, pltbutils_sc, true);
  -- waitclks(full, '1', sys_clk, pltbutils_sc, true, 1 ms);
  ---------------------------------------------------------------------------- 
  procedure waitsig(
    signal   s                  : in    integer;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    v_timeout_time := now + timeout;
    l1 : loop
      waitclks(1, clk, pltbutils_sc, falling, timeout);
      exit l1 when s = value or now >= v_timeout_time;
    end loop;
    if now >= v_timeout_time then
      assert false
      report "waitsig() timeout"
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    std_logic;
    constant value              : in    std_logic;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    v_timeout_time := now + timeout;
    l1 : loop
      waitclks(1, clk, pltbutils_sc, falling, timeout);
      exit l1 when s = value or now >= v_timeout_time;
    end loop;
    if now >= v_timeout_time then
      assert false
      report "waitsig() timeout"
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    std_logic;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_value            : std_logic;
    variable v_timeout_time     : time;
  begin
    case value is
      when 0      => v_value := '0';
      when 1      => v_value := '1';
      when others => v_value := 'X';
    end case;
    if v_value /= 'X' then
      waitsig(s, v_value, clk,
              pltbutils_sc, falling, timeout);
    else
      assert false
        report "waitsig() illegal value to wait for: " & integer'image(value)
        severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    std_logic_vector;
    constant value              : in    std_logic_vector;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    v_timeout_time := now + timeout;
    l1 : loop
      waitclks(1, clk, pltbutils_sc, falling, timeout);
      exit l1 when s = value or now >= v_timeout_time;
    end loop;
    if now >= v_timeout_time then
      assert false
      report "waitsig() timeout"
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    std_logic_vector;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    waitsig(s, std_logic_vector(to_unsigned(value, s'length)), clk,
            pltbutils_sc, falling, timeout);
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    unsigned;
    constant value              : in    unsigned;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    v_timeout_time := now + timeout;
    l1 : loop
      waitclks(1, clk, pltbutils_sc, falling, timeout);
      exit l1 when s = value or now >= v_timeout_time;
    end loop;
    if now >= v_timeout_time then
      assert false
      report "waitsig() timeout"
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    unsigned;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    waitsig(s, to_unsigned(value, s'length), clk,
            pltbutils_sc, falling, timeout);
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    signed;
    constant value              : in    signed;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    v_timeout_time := now + timeout;
    l1 : loop
      waitclks(1, clk, pltbutils_sc, falling, timeout);
      exit l1 when s = value or now >= v_timeout_time;
    end loop;
    if now >= v_timeout_time then
      assert false
      report "waitsig() timeout"
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure waitsig;
 
  procedure waitsig(
    signal   s                  : in    signed;
    constant value              : in    integer;
    signal   clk                : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t;
    constant falling            : in    boolean := false;
    constant timeout            : in    time    := C_PLTBUTILS_TIMEOUT
  ) is
    variable v_timeout_time     : time;
  begin
    waitsig(s, to_signed(value, s'length), clk,
            pltbutils_sc, falling, timeout);
  end procedure waitsig;
 
  ----------------------------------------------------------------------------
  -- check
  --
  -- procedure check(
  --  constant rpt              : in    string;
  --  constant data             : in    integer|std_logic|std_logic_vector|unsigned|signed;
  --  constant expected         : in    integer|std_logic|std_logic_vector|unsigned|signed;
  --  signal   pltbutils_sc     : out   pltbutils_sc_t
  --  )
  --
  -- procedure check(
  --  constant rpt              : in    string;
  --  constant data             : in    std_logic_vector;
  --  constant expected         : in    std_logic_vector;
  --  constant mask             : in    std_logic_vector;
  --  signal   pltbutils_sc     : out   pltbutils_sc_t
  --  )
  --
  -- procedure check(
  --   constant rpt            : in    string;
  --   constant expr           : in    boolean;
  --   signal   pltbutils_sc   : out   pltbutils_sc_t
  -- )
  --
  -- Checks that the value of a signal or variable is equal to expected.
  -- If not equal, displays an error message and increments the error counter.
  --
  -- Arguments: 
  --   rpt                      Report message to be displayed in case of 
  --                            mismatch. 
  --                            It is recommended that the message is unique
  --                            and that it contains the name of the signal
  --                            or variable being checked. 
  --                            The message should NOT contain the expected 
  --                            value, becase check() prints that 
  --                            automatically.
  --
  --   data                     The signal or variable to be checked.
  --                            Supported types: integer, std_logic, 
  --                            std_logic_vector, unsigned, signed.
  --
  --   expected                 Expected value. 
  --                            Same type as data or integer.
  --
  --   mask                     Bit mask and:ed to data and expected 
  --                            before comparison.
  --                            Optional if data is std_logic_vector.
  --                            Not allowed for other types.
  --
  --   expr                     boolean expression for checking.
  --                            This makes it possible to check any kind of
  --                            expresion, not just equality.
  -- 
  --   pltbutils_sc             PlTbUtils' global status- and control signal.
  --                            Must be set to the name pltbutils_sc.
  --
  -- Examples:
  -- check("dat_o after reset", dat_o, 0, pltbutils_sc);
  -- -- With mask:
  -- check("Status field in reg_o after start", reg_o, x"01", x"03", pltbutils_sc);
  -- -- Boolean expression:
  -- check("Counter after data burst", cnt_o > 10, pltbutils_sc);
  ----------------------------------------------------------------------------
  -- check integer
  procedure check(
    constant rpt                : in    string;
    constant data               : in    integer;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if data   /= expected then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt &
             "; Data=" & str(data) &
             " Expected=" & str(expected) &
             " " & --str(character'(lf)) &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHLD-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  -- check std_logic
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic;
    constant expected           : in    std_logic;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if data /= expected   then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt   &
             "; Data=" & str(data) &
             " Expected=" & str(expected) &
             " " & --str(character'(lf)) &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHLD-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  -- check std_logic against integer
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
    variable v_expected : std_logic;
  begin
    if expected = 0 then
      check(rpt , data, std_logic'('0'), pltbutils_sc);
    elsif expected = 1 then
      check(rpt , data, std_logic'('1'), pltbutils_sc);
    else
      v_pltbutils_chk_cnt.inc; -- VHDL-2002
      --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt &
             "; Data=" & str(data) &
             " Expected=" & str(expected) &
             " " & --str(character'(lf)) &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHLD-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
      pltbutils_sc_update(pltbutils_sc);
    end if;
  end procedure check;
 
  -- check std_logic_vector
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    std_logic_vector;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if data   /= expected   then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt   &
             "; Data=" & hxstr(data, "0x") &
             " Expected=" & hxstr(expected, "0x") &
             " " & --str('lf') &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  -- check std_logic_vector with mask
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    std_logic_vector;
    constant mask               : in    std_logic_vector;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if (data  and mask) /= (expected and mask) then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt &
             "; Data=" & hxstr(data, "0x") &
             " Expected=" & hxstr(expected, "0x") &
             " Mask=" & hxstr(mask, "0x") &
             " " & --str('lf') &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  -- check std_logic_vector against integer
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    check(rpt, data, std_logic_vector(to_signed(expected, data'length)), pltbutils_sc);
  end procedure check;
 
  -- check std_logic_vector with mask against integer
  procedure check(
    constant rpt                : in    string;
    constant data               : in    std_logic_vector;
    constant expected           : in    integer;
    constant mask               : in    std_logic_vector;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    check(rpt, data, std_logic_vector(to_signed(expected, data'length)), mask, pltbutils_sc);
  end procedure check;
 
  -- check unsigned
  procedure check(
    constant rpt                : in    string;
    constant data               : in    unsigned;
    constant expected           : in    unsigned;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if data   /= expected   then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt   &
             "; Data=" & hxstr(data, "0x") &
             " Expected=" & hxstr(expected, "0x") &
             " " & --str('lf') &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  -- check unsigned against integer
  procedure check(
    constant rpt                : in    string;
    constant data               : in    unsigned;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    check(rpt, data, to_unsigned(expected, data'length), pltbutils_sc);
  end procedure check;
 
  -- check signed
  procedure check(
    constant rpt                : in    string;
    constant data               : in    signed;
    constant expected           : in    signed;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if data /= expected   then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt   &
             "; Data=" & hxstr(data, "0x") &
             " Expected=" & hxstr(expected, "0x") &
             " " & --str('lf') &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  -- check signed against integer
  -- TODO: find the bug reported by tb_pltbutils when expected   is negative (-1):
  --       ** Error: (vsim-86) numstd_conv_unsigned_nu: NATURAL arg value is negative (-1)
  procedure check(
    constant rpt                : in    string;
    constant data               : in    signed;
    constant expected           : in    integer;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    check(rpt, data, to_signed(expected, data'length), pltbutils_sc);
  end procedure check;
 
  -- check with boolean expression
  -- Check signal or variable with a boolean expression as argument C_EXPR.
  -- This allowes any kind of check.
  procedure check(
    constant rpt                : in    string;
    constant expr               : in    boolean;
    signal   pltbutils_sc       : out   pltbutils_sc_t
  ) is
  begin
    v_pltbutils_chk_cnt.inc; -- VHDL-2002
    --v_pltbutils_chk_cnt := v_pltbutils_chk_cnt + 1; -- VHDL-1993
    if not expr then
      assert false
      report "Check " &
             str(v_pltbutils_chk_cnt.value) & -- VHDL-2002
             --str(v_pltbutils_chk_cnt) & -- VHDL-1993
             "; " & rpt   &
             " " & --str('lf') &
             "  in test " &
             str(v_pltbutils_test_num.value) & -- VHDL-2002
             --str(v_pltbutils_test_num) & -- VHDL-1993
             " " &
             v_pltbutils_test_name.value -- VHDL-2002
             --v_pltbutils_test_name -- VHDL-1993
      severity error;
      v_pltbutils_err_cnt.inc; -- VHDL-2002
      --v_pltbutils_err_cnt := v_pltbutils_err_cnt + 1; -- VHDL-1993
    end if;
    pltbutils_sc_update(pltbutils_sc);
  end procedure check;
 
  ----------------------------------------------------------------------------
  -- to_ascending
  --
  -- function to_ascending(
  --  constant s                  : std_logic_vector
  -- ) return std_logic_vector;
  --
  -- function to_ascending(
  --  constant s                  : unsigned
  -- ) return unsigned
  --
  -- function to_ascending(
  --  constant s                  : signed
  -- ) return signed;
  --
  -- Converts a signal or variable to ascending range ("to-range").
  -- The argument s can have ascending or descending range.
  ----------------------------------------------------------------------------
  function to_ascending(
    constant s                  : std_logic_vector
  ) return std_logic_vector is
    variable r : std_logic_vector(s'low to s'high);
  begin
    for i in r'range loop
      r(i) := s(i);
    end loop;
    return r;
  end function to_ascending;
 
  function to_ascending(
    constant s                  : unsigned
  ) return unsigned is
    variable r : unsigned(s'low to s'high);
  begin
    for i in r'range loop
      r(i) := s(i);
    end loop;
    return r;
  end function to_ascending;
 
  function to_ascending(
    constant s                  : signed
  ) return signed is
    variable r : signed(s'low to s'high);
  begin
    for i in r'range loop
      r(i) := s(i);
    end loop;
    return r;
  end function to_ascending;
 
  ----------------------------------------------------------------------------
  -- to_descending
  --
  -- function to_descending(
  --  constant s                  : std_logic_vector
  -- ) return std_logic_vector;
  --
  -- function to_descending(
  --  constant s                  : unsigned
  -- ) return unsigned
  --
  -- function to_descending(
  --  constant s                  : signed
  -- ) return signed;
  --
  -- Converts a signal or variable to descending range ("downto-range").
  -- The argument s can have ascending or descending range.
  ----------------------------------------------------------------------------
  function to_descending(
    constant s                  : std_logic_vector
  ) return std_logic_vector is
    variable r : std_logic_vector(s'high downto s'low);
  begin
    for i in r'range loop
      r(i) := s(i);
    end loop;
    return r;
  end function to_descending;
 
  function to_descending(
    constant s                  : unsigned
  ) return unsigned is
    variable r : unsigned(s'high downto s'low);
  begin
    for i in r'range loop
      r(i) := s(i);
    end loop;
    return r;
  end function to_descending;
 
  function to_descending(
    constant s                  : signed
  ) return signed is
    variable r : signed(s'high downto s'low);
  begin
    for i in r'range loop
      r(i) := s(i);
    end loop;
    return r;
  end function to_descending;
 
  ----------------------------------------------------------------------------
  -- hxstr
  -- function hxstr(
  --  constant s                  : std_logic_vector;
  --  constant prefix             : string := ""
  -- ) return string;
  --
  -- function hxstr(
  --  constant s                  : unsigned;
  --  constant prefix             : string := ""
  -- ) return string;
  --
  -- function hxstr(
  --  constant s                  : signed;
  --  constant prefix             : string := ""
  -- ) return string;
  --
  -- Converts a signal to a string in hexadecimal format.
  -- An optional prefix can be specified, e.g. "0x".
  --
  -- The signal can have ascending range ( "to-range" ) or descending range 
  -- ("downto-range").
  --
  -- hxstr is a wrapper function for hstr in txt_util.
  -- hstr only support std_logic_vector with descending range.
  --
  -- Examples:
  -- print("value=" & hxstr(s));
  -- print("value=" & hxstr(s, "0x"));
  ----------------------------------------------------------------------------
  function hxstr(
    constant s                  : std_logic_vector;
    constant prefix             : string := ""
  ) return string is
  begin
    return prefix & hstr(to_descending(s));
  end function hxstr;
 
  function hxstr(
    constant s                  : unsigned;
    constant prefix             : string := ""
  ) return string is
  begin
    return prefix & hstr(to_descending(std_logic_vector(s)));
  end function hxstr;
 
  function hxstr(
    constant s                  : signed;
    constant prefix             : string := ""
  ) return string is
  begin
    return prefix & hstr(to_descending(std_logic_vector(s)));
  end function hxstr;
 
  ----------------------------------------------------------------------------
  -- pltbutils internal procedure(s), called from other pltbutils procedures.
  -- Do not to call this/these from user's code.
  -- This/these procedures are undocumented in the specification on purpose.
  ----------------------------------------------------------------------------
  procedure pltbutils_sc_update(
              signal pltbutils_sc : out pltbutils_sc_t
            ) is
  begin
    -- VHDL-2002:
    pltbutils_sc.test_num   <= v_pltbutils_test_num.value;
    print(pltbutils_sc.test_name, v_pltbutils_test_name.value);
    print(pltbutils_sc.info, v_pltbutils_info.value);
    pltbutils_sc.chk_cnt    <= v_pltbutils_chk_cnt.value;
    pltbutils_sc.err_cnt    <= v_pltbutils_err_cnt.value;
    pltbutils_sc.stop_sim   <= v_pltbutils_stop_sim.value;
    -- VHDL-1993:
    --pltbutils_sc.test_num   <= v_pltbutils_test_num;
    --print(pltbutils_sc.test_name, v_pltbutils_test_name);
    --print(pltbutils_sc.info, v_pltbutils_info);
    --pltbutils_sc.chk_cnt    <= v_pltbutils_chk_cnt;
    --pltbutils_sc.err_cnt    <= v_pltbutils_err_cnt;
    --pltbutils_sc.stop_sim   <= v_pltbutils_stop_sim;
  end procedure pltbutils_sc_update;
 
end package body pltbutils_func_pkg;

Line No.	Rev	Author	Line
1	2	pela	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- PlTbUtils Fuctions and Procedures Package ----`
4			`---- ----`
5			`---- This file is part of the PlTbUtils project ----`
6			`---- http://opencores.org/project,pltbutils ----`
7			`---- ----`
8			`---- Description: ----`
9			`---- PlTbUtils is a collection of functions, procedures and ----`
10			`---- components for easily creating stimuli and checking response ----`
11			`---- in automatic self-checking testbenches. ----`
12			`---- ----`
13			`---- This file defines fuctions and procedures for controlling ----`
14			`---- stimuli to a DUT and checking response. ----`
15			`---- ----`
16			`---- To Do: ----`
17			`---- - ----`
18			`---- ----`
19			`---- Author(s): ----`
20			`---- - Per Larsson, pela@opencores.org ----`
21			`---- ----`
22			`----------------------------------------------------------------------`
23			`---- ----`
24			`---- Copyright (C) 2013 Authors and OPENCORES.ORG ----`
25			`---- ----`
26			`---- This source file may be used and distributed without ----`
27			`---- restriction provided that this copyright statement is not ----`
28			`---- removed from the file and that any derivative work contains ----`
29			`---- the original copyright notice and the associated disclaimer. ----`
30			`---- ----`
31			`---- This source file is free software; you can redistribute it ----`
32			`---- and/or modify it under the terms of the GNU Lesser General ----`
33			`---- Public License as published by the Free Software Foundation; ----`
34			`---- either version 2.1 of the License, or (at your option) any ----`
35			`---- later version. ----`
36			`---- ----`
37			`---- This source is distributed in the hope that it will be ----`
38			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
39			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
40			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
41			`---- details. ----`
42			`---- ----`
43			`---- You should have received a copy of the GNU Lesser General ----`
44			`---- Public License along with this source; if not, download it ----`
45			`---- from http://www.opencores.org/lgpl.shtml ----`
46			`---- ----`
47			`----------------------------------------------------------------------`
48			`library ieee;`
49			`use ieee.std_logic_1164.all;`
50			`use ieee.numeric_std.all;`
51			`use std.textio.all;`
52			`use std.env.all; -- VHDL-2008`
53			`use work.txt_util.all;`
54			`use work.pltbutils_type_pkg.all; -- Use for VHDL-2002, comment out for VHDL-93`
55
56			`package pltbutils_func_pkg is`
57
58			`-- See the package body for a description of the functions and procedures.`
59			`constant C_PLTBUTILS_STRLEN : natural := 80;`
60			`constant C_PLTBUTILS_TIMEOUT : time := 10 sec;`
61			`constant C_WAIT_BEFORE_STOP_TIME : time := 1 us;`
62
63			`-- Counters for number of checks and number of errors`
64			`-- VHDL-2002:`
65			`shared variable v_pltbutils_test_num : pltbutils_p_integer_t;`
66			`shared variable v_pltbutils_test_name : pltbutils_p_string_t;`
67			`shared variable v_pltbutils_info : pltbutils_p_string_t;`
68			`shared variable v_pltbutils_chk_cnt : pltbutils_p_integer_t;`
69			`shared variable v_pltbutils_err_cnt : pltbutils_p_integer_t;`
70			`shared variable v_pltbutils_stop_sim : pltbutils_p_std_logic_t;`
71			`-- VHDL-1993:`
72			`--shared variable v_pltbutils_test_num : natural := 0;`
73			`--shared variable v_pltbutils_test_name : string(1 to C_PLTBUTILS_STRLEN) := (others => ' ');`
74			`--shared variable v_pltbutils_info : string(1 to C_PLTBUTILS_STRLEN) := (others => ' ');`
75			`--shared variable v_pltbutils_chk_cnt : natural := 0;`
76			`--shared variable v_pltbutils_err_cnt : natural := 0;`
77			`--shared variable v_pltbutils_stop_sim : std_logic := '0';`
78
79			`-- Global status- and control signal`
80			`type pltbutils_sc_t is`
81			`record`
82			`test_num : natural;`
83			`test_name : string(1 to C_PLTBUTILS_STRLEN);`
84			`info : string(1 to C_PLTBUTILS_STRLEN);`
85			`chk_cnt : natural;`
86			`err_cnt : natural;`
87			`stop_sim : std_logic;`
88			`end record;`
89			`signal pltbutils_sc : pltbutils_sc_t;`
90
91			`-- startsim`
92			`procedure startsim(`
93			`constant testcase_name : in string;`
94			`signal pltbutils_sc : out pltbutils_sc_t`
95			`);`
96
97			`-- endsim`
98			`procedure endsim(`
99			`signal pltbutils_sc : out pltbutils_sc_t;`
100			`constant show_success_fail : in boolean := false;`
101			`constant force : in boolean := false`
102			`);`
103
104			`-- testname`
105			`procedure testname(`
106			`constant num : in integer := -1;`
107			`constant name : in string;`
108			`signal pltbutils_sc : out pltbutils_sc_t`
109			`);`
110			`procedure testname(`
111			`constant name : in string;`
112			`signal pltbutils_sc : out pltbutils_sc_t`
113			`);`
114
115			`-- print, printv, print2`
116			`procedure print(`
117	6	pela	`constant active : in boolean;`
118	2	pela	`signal s : out string;`
119			`constant txt : in string`
120			`);`
121	6	pela	`procedure print(`
122			`signal s : out string;`
123			`constant txt : in string`
124			`);`
125	2	pela	`procedure printv(`
126	6	pela	`constant active : in boolean;`
127	2	pela	`variable s : out string;`
128			`constant txt : in string`
129			`);`
130			`procedure printv(`
131	6	pela	`variable s : out string;`
132			`constant txt : in string`
133			`);`
134			`procedure printv(`
135			`constant active : in boolean;`
136	2	pela	`variable s : inout pltbutils_p_string_t;`
137			`constant txt : in string`
138			`);`
139	6	pela	`procedure printv(`
140			`variable s : inout pltbutils_p_string_t;`
141			`constant txt : in string`
142			`);`
143	2	pela	`procedure print(`
144	6	pela	`constant active : in boolean;`
145	2	pela	`signal pltbutils_sc : out pltbutils_sc_t;`
146			`constant txt : in string`
147			`);`
148	6	pela	`procedure print(`
149			`signal pltbutils_sc : out pltbutils_sc_t;`
150			`constant txt : in string`
151			`);`
152	2	pela	`procedure print2(`
153	6	pela	`constant active : in boolean;`
154	2	pela	`signal s : out string;`
155			`constant txt : in string`
156			`);`
157			`procedure print2(`
158	6	pela	`signal s : out string;`
159			`constant txt : in string`
160			`);`
161			`procedure print2(`
162			`constant active : in boolean;`
163	2	pela	`signal pltbutils_sc : out pltbutils_sc_t;`
164			`constant txt : in string`
165			`);`
166	6	pela	`procedure print2(`
167			`signal pltbutils_sc : out pltbutils_sc_t;`
168			`constant txt : in string`
169			`);`
170	2	pela
171			`-- waitclks`
172			`procedure waitclks(`
173			`constant N : in natural;`
174			`signal clk : in std_logic;`
175			`signal pltbutils_sc : out pltbutils_sc_t;`
176			`constant falling : in boolean := false;`
177			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
178			`);`
179
180	6	pela	`-- waitsig`
181			`procedure waitsig(`
182			`signal s : in integer;`
183			`constant value : in integer;`
184			`signal clk : in std_logic;`
185			`signal pltbutils_sc : out pltbutils_sc_t;`
186			`constant falling : in boolean := false;`
187			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
188			`);`
189			`procedure waitsig(`
190			`signal s : in std_logic;`
191			`constant value : in std_logic;`
192			`signal clk : in std_logic;`
193			`signal pltbutils_sc : out pltbutils_sc_t;`
194			`constant falling : in boolean := false;`
195			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
196			`);`
197			`procedure waitsig(`
198			`signal s : in std_logic;`
199			`constant value : in integer;`
200			`signal clk : in std_logic;`
201			`signal pltbutils_sc : out pltbutils_sc_t;`
202			`constant falling : in boolean := false;`
203			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
204			`);`
205			`procedure waitsig(`
206			`signal s : in std_logic_vector;`
207			`constant value : in std_logic_vector;`
208			`signal clk : in std_logic;`
209			`signal pltbutils_sc : out pltbutils_sc_t;`
210			`constant falling : in boolean := false;`
211			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
212			`);`
213			`procedure waitsig(`
214			`signal s : in std_logic_vector;`
215			`constant value : in integer;`
216			`signal clk : in std_logic;`
217			`signal pltbutils_sc : out pltbutils_sc_t;`
218			`constant falling : in boolean := false;`
219			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
220			`);`
221			`procedure waitsig(`
222			`signal s : in unsigned;`
223			`constant value : in unsigned;`
224			`signal clk : in std_logic;`
225			`signal pltbutils_sc : out pltbutils_sc_t;`
226			`constant falling : in boolean := false;`
227			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
228			`);`
229			`procedure waitsig(`
230			`signal s : in unsigned;`
231			`constant value : in integer;`
232			`signal clk : in std_logic;`
233			`signal pltbutils_sc : out pltbutils_sc_t;`
234			`constant falling : in boolean := false;`
235			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
236			`);`
237			`procedure waitsig(`
238			`signal s : in signed;`
239			`constant value : in signed;`
240			`signal clk : in std_logic;`
241			`signal pltbutils_sc : out pltbutils_sc_t;`
242			`constant falling : in boolean := false;`
243			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
244			`);`
245			`procedure waitsig(`
246			`signal s : in signed;`
247			`constant value : in integer;`
248			`signal clk : in std_logic;`
249			`signal pltbutils_sc : out pltbutils_sc_t;`
250			`constant falling : in boolean := false;`
251			`constant timeout : in time := C_PLTBUTILS_TIMEOUT`
252			`);`
253
254	2	pela	`-- check`
255			`procedure check(`
256			`constant rpt : in string;`
257			`constant data : in integer;`
258			`constant expected : in integer;`
259			`signal pltbutils_sc : out pltbutils_sc_t`
260			`);`
261			`procedure check(`
262			`constant rpt : in string;`
263			`constant data : in std_logic;`
264			`constant expected : in std_logic;`
265			`signal pltbutils_sc : out pltbutils_sc_t`
266			`);`
267			`procedure check(`
268			`constant rpt : in string;`
269			`constant data : in std_logic;`
270			`constant expected : in integer;`
271			`signal pltbutils_sc : out pltbutils_sc_t`
272			`);`
273			`procedure check(`
274			`constant rpt : in string;`
275			`constant data : in std_logic_vector;`
276			`constant expected : in std_logic_vector;`
277			`signal pltbutils_sc : out pltbutils_sc_t`
278			`);`
279			`procedure check(`
280			`constant rpt : in string;`
281			`constant data : in std_logic_vector;`
282			`constant expected : in std_logic_vector;`
283			`constant mask : in std_logic_vector;`
284			`signal pltbutils_sc : out pltbutils_sc_t`
285			`);`
286			`procedure check(`
287			`constant rpt : in string;`
288			`constant data : in std_logic_vector;`
289			`constant expected : in integer;`
290			`signal pltbutils_sc : out pltbutils_sc_t`
291			`);`
292			`procedure check(`
293			`constant rpt : in string;`
294			`constant data : in std_logic_vector;`
295			`constant expected : in integer;`
296			`constant mask : in std_logic_vector;`
297			`signal pltbutils_sc : out pltbutils_sc_t`
298			`);`
299			`procedure check(`
300			`constant rpt : in string;`
301			`constant data : in unsigned;`
302			`constant expected : in unsigned;`
303			`signal pltbutils_sc : out pltbutils_sc_t`
304			`);`
305			`procedure check(`
306			`constant rpt : in string;`
307			`constant data : in unsigned;`
308			`constant expected : in integer;`
309			`signal pltbutils_sc : out pltbutils_sc_t`
310			`);`
311			`procedure check(`
312			`constant rpt : in string;`
313			`constant data : in signed;`
314			`constant expected : in signed;`
315			`signal pltbutils_sc : out pltbutils_sc_t`
316			`);`
317			`procedure check(`
318			`constant rpt : in string;`
319			`constant data : in signed;`
320			`constant expected : in integer;`
321			`signal pltbutils_sc : out pltbutils_sc_t`
322			`);`
323			`procedure check(`
324			`constant rpt : in string;`
325			`constant expr : in boolean;`
326			`signal pltbutils_sc : out pltbutils_sc_t`
327			`);`
328	14	pela
329			`-- to_ascending`
330			`function to_ascending(`
331			`constant s : std_logic_vector`
332			`) return std_logic_vector;`
333			`function to_ascending(`
334			`constant s : unsigned`
335			`) return unsigned;`
336			`function to_ascending(`
337			`constant s : signed`
338			`) return signed;`
339	2	pela
340	14	pela	`-- to_descending`
341			`function to_descending(`
342			`constant s : std_logic_vector`
343			`) return std_logic_vector;`
344			`function to_descending(`
345			`constant s : unsigned`
346			`) return unsigned;`
347			`function to_descending(`
348			`constant s : signed`
349			`) return signed;`
350
351			`-- hxstr`
352			`function hxstr(`
353			`constant s : std_logic_vector;`
354			`constant prefix : string := ""`
355			`) return string;`
356			`function hxstr(`
357			`constant s : unsigned;`
358			`constant prefix : string := ""`
359			`) return string;`
360			`function hxstr(`
361			`constant s : signed;`
362			`constant prefix : string := ""`
363			`) return string;`
364
365	2	pela	`-- pltbutils internal procedure(s), do not call from user's code`
366			`procedure pltbutils_sc_update(`
367			`signal pltbutils_sc : out pltbutils_sc_t`
368			`);`
369
370			`end package pltbutils_func_pkg;`
371
372			`package body pltbutils_func_pkg is`
373
374			`----------------------------------------------------------------------------`
375			`-- startsim`
376			`--`
377			`-- procedure startsim(`
378			`-- constant testcase_name : in string;`
379			`-- signal pltbutils_sc : out pltbutils_sc_t`
380			`-- )`
381			`--`
382			`-- Displays a message at start of simulation message, and initializes`
383			`-- PlTbUtils' global status and control signal.`
384			`-- Call startsim() only once.`
385			`--`
386			`-- Arguments:`
387			`-- testcase_name Name of the test case, e.g. "tc1".`
388			`--`
389			`-- pltbutils_sc PlTbUtils' global status- and control signal.`
390			`-- Must be set to pltbutils_sc.`
391			`--`
392			`-- NOTE:`
393			`-- The start-of-simulation message is not only intended to be informative`
394			`-- for humans. It is also intended to be searched for by scripts,`
395			`-- e.g. for collecting results from a large number of regression tests.`
396			`-- For this reason, the message must be consistent and unique.`
397			`--`
398			`-- DO NOT MODIFY the message "--- START OF SIMULATION ---".`
399			`-- DO NOT OUTPUT AN IDENTICAL MESSAGE anywhere else.`
400			`--`
401			`-- Example:`
402			`-- startsim("tc1", pltbutils_sc);`
403			`----------------------------------------------------------------------------`
404			`procedure startsim(`
405			`constant testcase_name : in string;`
406			`signal pltbutils_sc : out pltbutils_sc_t`
407			`) is`
408			`variable dummy : integer;`
409			`begin`
410			`printv(v_pltbutils_info, testcase_name);`
411			`print(lf & "--- START OF SIMULATION ---");`
412			`print("Testcase: " & testcase_name);`
413			`print(time'image(now));`
414			`-- VHDL-2002:`
415			`v_pltbutils_stop_sim.clr;`
416			`v_pltbutils_test_num.clr;`
417			`v_pltbutils_test_name.set("START OF SIMULATION");`
418			`v_pltbutils_chk_cnt.clr;`
419			`v_pltbutils_err_cnt.clr;`
420			`pltbutils_sc_update(pltbutils_sc);`
421			`-- VHDL-1993:`
422			`--v_pltbutils_stop_sim := '0';`
423			`--v_pltbutils_test_num := 0;`
424			`--printv(v_pltbutils_test_name, "START OF SIMULATION");`
425			`--v_pltbutils_chk_cnt := 0;`
426			`--v_pltbutils_err_cnt := 0;`
427			`--pltbutils_sc_update(pltbutils_sc);`
428			`end procedure startsim;`
429
430			`----------------------------------------------------------------------------`
431			`-- endsim`
432			`--`
433			`-- procedure endsim(`
434			`-- signal pltbutils_sc : out pltbutils_sc_t;`
435			`-- constant show_success_fail : in boolean := false;`
436			`-- constant force : in boolean := false`
437			`-- )`
438			`--`
439			`-- Displays a message at end of simulation message, presents the simulation`
440			`-- results, and stops the simulation.`
441			`-- Call endsim() it only once.`
442			`--`
443			`-- Arguments:`
444			`-- pltbutils_sc PlTbUtils' global status- and control signal.`
445			`-- Must be set to pltbutils_sc.`
446			`--`
447			`-- show_success_fail If true, endsim() shows "* SUCCESS *",`
448			`-- "* FAIL ", or " NO CHECKS *".`
449			`-- Optional, default is false.`
450			`--`
451			`-- force If true, forces the simulation to stop using an`
452			`-- assert failure statement. Use this option only`
453			`-- if the normal way of stopping the simulation`
454			`-- doesn't work (see below).`
455			`-- Optional, default is false.`
456			`--`
457			`-- The testbench should be designed so that all clocks stop when endsim()`
458			`-- sets the signal stop_sim to '1'. This should stop the simulator.`
459			`-- In some cases, that doesn't work, then set the force argument to true, which`
460			`-- causes a false assert failure, which should stop the simulator.`
461			`-- Scripts searching transcript logs for errors and failures, should ignore`
462			`-- the failure with "--- FORCE END OF SIMULATION ---" as part of the report.`
463			`--`
464			`-- NOTE:`
465			`-- The end-of-simulation messages and success/fail messages are not only`
466			`-- intended to be informative for humans. They are also intended to be`
467			`-- searched for by scripts, e.g. for collecting results from a large number`
468			`-- of regression tests.`
469			`-- For this reason, the message must be consistent and unique.`
470			`--`
471			`-- DO NOT MODIFY the messages "--- END OF SIMULATION ---",`
472			`-- "* SUCCESS ", " FAIL ", " NO CHECKS *".`
473			`-- DO NOT OUTPUT IDENTICAL MESSAGES anywhere else.`
474			`--`
475			`-- Examples:`
476			`-- endsim(pltbutils_sc);`
477			`-- endsim(pltbutils_sc, true);`
478			`-- endsim(pltbutils_sc, true, true);`
479			`----------------------------------------------------------------------------`
480			`procedure endsim(`
481			`signal pltbutils_sc : out pltbutils_sc_t;`
482			`constant show_success_fail : in boolean := false;`
483			`constant force : in boolean := false`
484			`) is`
485			`variable l : line;`
486			`begin`
487			`printv(v_pltbutils_info, "");`
488			`print(lf & "--- END OF SIMULATION ---");`
489			`print("Note: the results presented below are based on the PlTbUtil's check() procedure calls.");`
490			`print(" The design may contain more errors, for which there are no check() calls.");`
491			`write(l, now, right, 14);`
492			`writeline(output, l);`
493			`write(l, v_pltbutils_chk_cnt.value, right, 11); -- VHDL-2002`
494			`--write(l, v_pltbutils_chk_cnt, right, 11); -- VHDL-1993`
495			`write(l, string'(" Checks"));`
496			`writeline(output, l);`
497			`write(l, v_pltbutils_err_cnt.value, right, 11); -- VHDL-2002`
498			`--write(l, v_pltbutils_chk_cnt, right, 11); -- VHDL-1993`
499			`write(l, string'(" Errors"));`
500			`writeline(output, l);`

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