| 1 |
2 |
pela |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- PlTbUtils Testbench Template ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the PlTbUtils project ----
|
| 6 |
|
|
---- http://opencores.org/project,pltbutils ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description: ----
|
| 9 |
|
|
---- PlTbUtils is a collection of functions, procedures and ----
|
| 10 |
|
|
---- components for easily creating stimuli and checking response ----
|
| 11 |
|
|
---- in automatic self-checking testbenches. ----
|
| 12 |
|
|
---- ----
|
| 13 |
|
|
---- This file is a template, which can be used as a base when ----
|
| 14 |
|
|
---- testbenches which use PlTbUtils. ----
|
| 15 |
|
|
---- Copy this file to your preferred location and rename the ----
|
| 16 |
|
|
---- copied file and its contents, by replacing the word ----
|
| 17 |
|
|
---- "template" with a name for your design. ----
|
| 18 |
|
|
---- Also remove informative comments enclosed in < ... > . ----
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
---- ----
|
| 21 |
|
|
---- To Do: ----
|
| 22 |
|
|
---- - ----
|
| 23 |
|
|
---- ----
|
| 24 |
|
|
---- Author(s): ----
|
| 25 |
|
|
---- - Per Larsson, pela@opencores.org ----
|
| 26 |
|
|
---- ----
|
| 27 |
|
|
----------------------------------------------------------------------
|
| 28 |
|
|
---- ----
|
| 29 |
|
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
|
| 30 |
|
|
---- ----
|
| 31 |
|
|
---- This source file may be used and distributed without ----
|
| 32 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 33 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 34 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 35 |
|
|
---- ----
|
| 36 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 37 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 38 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 39 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 40 |
|
|
---- later version. ----
|
| 41 |
|
|
---- ----
|
| 42 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 43 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 44 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 45 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 46 |
|
|
---- details. ----
|
| 47 |
|
|
---- ----
|
| 48 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 49 |
|
|
---- Public License along with this source; if not, download it ----
|
| 50 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 51 |
|
|
---- ----
|
| 52 |
|
|
----------------------------------------------------------------------
|
| 53 |
|
|
library ieee;
|
| 54 |
|
|
use ieee.std_logic_1164.all;
|
| 55 |
|
|
use std.textio.all;
|
| 56 |
|
|
use work.txt_util.all;
|
| 57 |
|
|
use work.pltbutils_func_pkg.all;
|
| 58 |
|
|
use work.pltbutils_comp_pkg.all;
|
| 59 |
|
|
-- < Template info: add more libraries here, if needed >
|
| 60 |
|
|
|
| 61 |
|
|
entity tb_template is
|
| 62 |
|
|
generic (
|
| 63 |
|
|
-- < Template info: add generics here if needed, or remove the generic block >
|
| 64 |
|
|
);
|
| 65 |
|
|
end entity tb_template;
|
| 66 |
|
|
|
| 67 |
|
|
architecture bhv of tb_template is
|
| 68 |
|
|
|
| 69 |
|
|
-- Simulation status- and control signals
|
| 70 |
|
|
signal test_num : integer;
|
| 71 |
|
|
-- VHDL-1993:
|
| 72 |
|
|
--signal test_name : string(pltbutils_test_name'range);
|
| 73 |
|
|
--signal info : string(pltbutils_info'range);
|
| 74 |
|
|
-- VHDL-2002:
|
| 75 |
|
|
signal test_name : string(pltbutils_sc.test_name'range);
|
| 76 |
|
|
signal info : string(pltbutils_sc.info'range);
|
| 77 |
|
|
|
| 78 |
|
|
signal checks : integer;
|
| 79 |
|
|
signal errors : integer;
|
| 80 |
|
|
signal stop_sim : std_logic;
|
| 81 |
|
|
|
| 82 |
|
|
-- DUT stimuli and response signals
|
| 83 |
|
|
signal clk : std_logic;
|
| 84 |
|
|
signal rst : std_logic;
|
| 85 |
|
|
-- < Template info: add more DUT stimuli and response signals here. >
|
| 86 |
|
|
|
| 87 |
|
|
begin
|
| 88 |
|
|
|
| 89 |
|
|
-- Simulation status and control for viewing in waveform window
|
| 90 |
|
|
-- VHDL-1993:
|
| 91 |
|
|
--test_num <= pltbutils_test_num;
|
| 92 |
|
|
--test_name <= pltbutils_test_name;
|
| 93 |
|
|
--checks <= pltbutils_chk_cnt;
|
| 94 |
|
|
--errors <= pltbutils_err_cnt;
|
| 95 |
|
|
-- VHDL-2002:
|
| 96 |
|
|
test_num <= pltbutils_sc.test_num;
|
| 97 |
|
|
test_name <= pltbutils_sc.test_name;
|
| 98 |
|
|
info <= pltbutils_sc.info;
|
| 99 |
|
|
checks <= pltbutils_sc.chk_cnt;
|
| 100 |
|
|
errors <= pltbutils_sc.err_cnt;
|
| 101 |
|
|
stop_sim <= pltbutils_sc.stop_sim;
|
| 102 |
|
|
|
| 103 |
|
|
|
| 104 |
|
|
dut0 : entity work.template
|
| 105 |
|
|
generic map (
|
| 106 |
|
|
-- < Template info: add DUT generics here, if any. >
|
| 107 |
|
|
)
|
| 108 |
|
|
port map (
|
| 109 |
|
|
clk_i => clk, -- Template example
|
| 110 |
|
|
rst_i => rst, -- Template example
|
| 111 |
|
|
-- < Template info: add more DUT ports here. >
|
| 112 |
|
|
);
|
| 113 |
|
|
|
| 114 |
|
|
clkgen0 : pltbutils_clkgen
|
| 115 |
|
|
generic map(
|
| 116 |
|
|
G_PERIOD => G_CLK_PERIOD
|
| 117 |
|
|
)
|
| 118 |
|
|
port map(
|
| 119 |
|
|
clk_o => clk,
|
| 120 |
|
|
stop_sim_i => stop_sim
|
| 121 |
|
|
);
|
| 122 |
|
|
|
| 123 |
|
|
tc0 : entity work.tc_example
|
| 124 |
|
|
generic map (
|
| 125 |
|
|
-- < Template info: add generics for testcase component here, if any. >
|
| 126 |
|
|
)
|
| 127 |
|
|
port map(
|
| 128 |
|
|
clk => clk, -- Template example
|
| 129 |
|
|
rst => rst, -- Template example
|
| 130 |
|
|
-- < Template info: add more ports for testcase component here. >
|
| 131 |
|
|
);
|
| 132 |
|
|
|
| 133 |
|
|
end architecture bhv;
|
