1 |
2 |
ldalmasso |
# PmodAD2Driver
|
2 |
|
|
|
3 |
|
|
Pmod AD2 Driver for the 4 Channels of 12-bit Analog-to-Digital Converter AD7991. The communication with the ADC uses the I2C protocol. User can specifies the I2C Clock Frequency (up to 400 kHz with the Fast Mode).
|
4 |
|
|
|
5 |
|
|

|
6 |
|
|
|
7 |
|
|
## Usage
|
8 |
|
|
|
9 |
|
|
User specifies inputs: I2C mode (i_mode), ADC Slave Address (i_addr), Configuration Byte (i_config_byte, write mode only) and the Last Read Cycle trigger (i_last_read, read mode only).
|
10 |
|
|
|
11 |
|
|
The i_enable signal can be triggered (set to '1') to begin transmission.
|
12 |
|
|
|
13 |
|
|
When started, the PmodAD2Driver executes the complete operation cycle (configurations or ADC conversions) independently of the new i_enable signal value.
|
14 |
|
|
|
15 |
|
|
At the end of the operation cycle, if the i_enable signal is still set to '1', the PmodAD2Driver executes the operation again with the current inputs.
|
16 |
|
|
|
17 |
|
|
The o_ready signal (set to '1') indicates the PmodAD2Driver is ready to process new operation. The o_ready signal is set to '0' to acknowledge the receipt.
|
18 |
|
|
|
19 |
|
|
The o_ready signal is set to '0' to acknowledge the receipt.
|
20 |
|
|
|
21 |
|
|
In Write mode, the PmodAD2Driver writes the Configuration byte into the ADC register and stop the transmission.
|
22 |
|
|
|
23 |
|
|
In Read mode, the PmodAD2Driver always reads 2-byte ADC conversion values channel-by-channel (according to ADC configuration).
|
24 |
|
|
|
25 |
|
|
The ADC value (o_adc_value) is available when its validity signal (o_adc_valid) is asserted.
|
26 |
|
|
|
27 |
|
|
In Read mode, while the i_last_read is NOT set to '1', the PmodAD2Driver execute the read operation.
|
28 |
|
|
|
29 |
|
|
ADC AD7991 has 2 I2C Addresses:
|
30 |
|
|
AD7991-0: 010 1000
|
31 |
|
|
AD7991-1: 010 1001
|
32 |
|
|
|
33 |
|
|
Configuration Register (8-bit Write Only)
|
34 |
|
|
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Bit |
|
35 |
|
|
|-----|-----|-----|-----|---------|------|-----------------|------------|-----|
|
36 |
|
|
| CH3 | CH2 | CH1 | CH0 | REF_SEL | FLTR | Bit Trial delay | Sample delay | Description |
|
37 |
|
|
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Default Value |
|
38 |
|
|
|
39 |
|
|
Configuration Register MSB Description
|
40 |
|
|
| D7 | D6 | D5 | D4 | Analog Input Channel |
|
41 |
|
|
|----|----|----|----|----------------------|
|
42 |
|
|
| 0 | 0 | 0 | 0 | No channel selected |
|
43 |
|
|
| 0 | 0 | 0 | 1 | Convert on VIN0 |
|
44 |
|
|
| 0 | 0 | 1 | 0 | Convert on VIN1 |
|
45 |
|
|
| 0 | 0 | 1 | 1 | Sequence between VIN0 and VIN1 |
|
46 |
|
|
| 0 | 1 | 0 | 0 | Convert on VIN2 |
|
47 |
|
|
| 0 | 1 | 0 | 1 | Sequence between VIN0 and VIN2 |
|
48 |
|
|
| 0 | 1 | 1 | 0 | Sequence between VIN1 and VIN2 |
|
49 |
|
|
| 0 | 1 | 1 | 1 | Sequence among VIN0, VIN1, and VIN2 |
|
50 |
|
|
| 1 | 0 | 0 | 0 | Convert on VIN3 |
|
51 |
|
|
| 1 | 0 | 0 | 1 | Sequence between VIN0 and VIN3 |
|
52 |
|
|
| 1 | 0 | 1 | 0 | Sequence between VIN1 and VIN3 |
|
53 |
|
|
| 1 | 0 | 1 | 1 | Sequence among VIN0, VIN1, and VIN3 |
|
54 |
|
|
| 1 | 1 | 0 | 0 | Sequence between VIN2 and VIN3 |
|
55 |
|
|
| 1 | 1 | 0 | 1 | Sequence among VIN0, VIN2, and VIN3 |
|
56 |
|
|
| 1 | 1 | 1 | 0 | Sequence among VIN1, VIN2, and VIN3 |
|
57 |
|
|
| 1 | 1 | 1 | 1 | Sequence among VIN0, VIN1, VIN2, and VIN3 |
|
58 |
|
|
|
59 |
|
|
Conversion Result Register (16-bit Read Only)
|
60 |
|
|
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|
61 |
|
|
|-----|-----|-------|-------|-----|-----|----|----|----|----|----|----|----|----|----|----|
|
62 |
|
|
| 0 | 0 | CHID1 | CHID0 | MSB | B10 | B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
|
63 |
|
|
|
64 |
|
|
## Signal Generator Pin Description
|
65 |
|
|
|
66 |
|
|
### Generics
|
67 |
|
|
|
68 |
|
|
| Name | Description |
|
69 |
|
|
| ---- | ----------- |
|
70 |
|
|
| sys_clock | System Input Clock Frequency (Hz) |
|
71 |
|
|
| i2c_clock | I2C Serial Clock Frequency (Standard Mode: 100 kHz, Fast Mode: 400 kHz) |
|
72 |
|
|
|
73 |
|
|
### Ports
|
74 |
|
|
|
75 |
|
|
| Name | Type | Description |
|
76 |
|
|
| ---- | ---- | ----------- |
|
77 |
|
|
| i_sys_clock | Input | System Input Clock |
|
78 |
|
|
| i_enable | Input | Module Enable ('0': Disable, '1': Enable) |
|
79 |
|
|
| i_mode | Input | Read or Write Mode ('0': Write, '1': Read) |
|
80 |
|
|
| i_addr | Input | ADC Address (7 bits) |
|
81 |
|
|
| i_config_byte | Input | ADC Configuration Byte (8 bits) |
|
82 |
|
|
| i_last_read | Input | Indicates the Last Read Operation ('0': Continue Read Cycle, '1': Last Read Cycle) |
|
83 |
|
|
| o_adc_valid | Output | ADC Read Value Valid ('0': Not Valid, '1': Valid) |
|
84 |
|
|
| o_adc_value | Output | ADC Read Value |
|
85 |
|
|
| o_ready | Output | ADC Ready Status ('0': NOT Ready, '1': Ready) |
|
86 |
|
|
| io_scl | In/Out | I2C Serial Clock ('0'-'Z'(as '1') values, working with Pull-Up) |
|
87 |
|
|
| io_sda | In/Out | I2C Serial Data ('0'-'Z'(as '1') values, working with Pull-Up) |
|