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[/] [potato/] [tags/] [v0.1/] [example/] [README] - Blame information for rev 7
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# Demo design for the Nexys 4 board
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This folder contains a design for a simple demo design using the Potato
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processor. It has been tested using Vivado 2014.4.
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## Quick Start
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In order to use the design, first import all source files from the folders
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`src/`, `soc/` and `example/` into your project.
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### Clocking
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Then add a clock generator using the Clocking Wizard. To seamlessly integrate
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it into the design, name it "clock_generator". Choose the following options:
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* Frequency Synthesis
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* Safe Clock Startup
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Set up two output clocks, `clk_out1` with frequency 50 MHz, and `clk_out2` with
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a frequency of 10 MHz. Rename the corresponding ports to `system_clk` and
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`timer_clk` respectively. Name the input clock `clk`.
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### Instruction memory
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Add a block RAM to use as instruction ROM using the Block Memory Generator.
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Choose "Single Port ROM" as memory type, set port A width to 32 bits and
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port A depth to 2048. Initialize it with your application binary and,
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optionally, fill the remaining memory locations with 0x00000013.
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### Test it!
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Now you can test it and hopefully it works :-)
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