OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [README] - Blame information for rev 61

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 skordal
# The Potato Processor
2
 
3
Potato is a simple processor for use in FPGAs, implementing the RV32I subset of the RISC-V ISA specification.
4
 
5
## Features
6
 
7
* Supports the full RV32I (RISC-V 32-bit integer subset) ISA.
8
* Additionally supports the csrr\* and sret instructions from the (previous) supervisor extension (draft).
9
* Includes an interface for the HTIF (Host/Target interface) registers, TOHOST and FROMHOST.
10
* Wishbone interface.
11
 
12
## Wishbone details
13
 
14
The wishbone interface for the processor is provided by the pp_wb_adapter module. Its details are as follows:
15
 
16 5 skordal
|-----------------------|---------------|
17 2 skordal
| Name                  | Value         |
18
| --------------------- | ------------- |
19
| Wishbone revision     | B4            |
20
| Interface type        | Master        |
21
| Address port width    | 32 bits       |
22
| Data port width       | 32 bits       |
23
| Data port granularity | 8 bits        |
24
| Maximum operand size  | 32 bits       |
25
| Endianess             | Little endian |
26
| Sequence of data xfer | Undefined     |
27 5 skordal
|---------------------------------------|
28 2 skordal
 
29
For all Wishbone interfaces included in this project, the Wishbone signals are prefixed with `wb` and suffixed by the
30
signal direction.
31
 
32
## Potato Processor Quick Start
33
 
34
To instantiate the processor, add the source files from the `src/` folder to your project. Use the `pp_potato` core to
35
instantiate a processor core with a Wishbone interface. Additional peripherals for use in Wishbone-based Potato systems
36
can be found in the `soc/` folder.
37
 
38
Use the `pp_core` module to instantiate a processor core with a more generic interface, for instance for use with block
39
memories. In this instance, connect the data and instruction memory ports directly to the block RAM modules/interfaces
40
and set the acknowledge inputs to `'1'`.
41
 
42
Interrupts are triggered when an IRQ signal is high and the corresponding mask bit is set in the control/status register.
43
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.