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[/] [potato/] [trunk/] [benchmarks/] [start.S] - Blame information for rev 16

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1 13 skordal
// The Potato Processor Benchmark Applications
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// (c) Kristian Klomsten Skordal 2015 
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// Report bugs and issues on 
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// This file contains startup and initialization code for the Potato benchmark
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// applications.
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#include "platform.h"
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.section .init
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.global _start
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_start:
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// Copies the .data section into the data memory section:
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.hidden copy_data
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copy_data:
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        la x1, __text_end       // Copy source address
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        la x2, __data_begin     // Copy destination address
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        la x3, __data_end       // Copy destination end address
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        beq x2, x3, 2f          // Skip if there is no data to copy
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1:
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        lw x4, (x1)
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        sw x4, (x2)
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        addi x1, x1, 4
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        addi x2, x2, 4
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        bne x2, x3, 1b          // Repeat as long as there is more data to copy
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2:
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.hidden clear_bss
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clear_bss:
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        la x1, __bss_begin
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        la x2, __bss_end
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        beq x1, x2, 2f          // Skip if there is no .bss section
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1:
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        sw x0, (x1)
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        addi x1, x1, 4
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        bne x1, x2, 1b
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2:
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.hidden set_evec
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set_evec:
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        // Set up an exception handler:
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        la x1, exception_handler_wrapper
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        csrw evec, x1
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.hidden call_main
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call_main:
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        la sp, __stack_top
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        jal main
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        csrw tohost, a0
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1:
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        j 1b
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.section .text
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.global exception_handler_wrapper
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exception_handler_wrapper:
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        // Save all registers that aren't saved by the IRQ handler function:
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        addi sp, sp, -64
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        sw ra, 0(sp)
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        sw t0, 4(sp)
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        sw t1, 8(sp)
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        sw t2, 12(sp)
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        sw t3, 16(sp)
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        sw t4, 20(sp)
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        sw t5, 24(sp)
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        sw t6, 28(sp)
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        sw a0, 32(sp)
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        sw a1, 36(sp)
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        sw a2, 40(sp)
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        sw a3, 44(sp)
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        sw a4, 48(sp)
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        sw a5, 52(sp)
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        sw a6, 56(sp)
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        sw a7, 60(sp)
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        csrr a0, cause
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        csrr a1, epc
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        jal exception_handler
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        // Restore the current state:
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        lw ra, 0(sp)
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        lw t0, 4(sp)
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        lw t1, 8(sp)
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        lw t2, 12(sp)
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        lw t3, 16(sp)
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        lw t4, 20(sp)
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        lw t5, 24(sp)
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        lw t6, 28(sp)
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        lw a0, 32(sp)
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        lw a1, 36(sp)
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        lw a2, 40(sp)
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        lw a3, 44(sp)
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        lw a4, 48(sp)
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        lw a5, 52(sp)
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        lw a6, 56(sp)
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        lw a7, 60(sp)
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        addi sp, sp, 64
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        sret
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