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skordal |
% The Potato Processor - Processor Datasheet
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% (c) Kristian Klomsten Skordal 2015 <skordal@opencores.org>
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% Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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\documentclass[10pt,a4paper]{article}
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\usepackage[pdftitle={The Potato Processor Datasheet},
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pdfauthor={Kristian Klomsten Skordal}]{hyperref}
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\usepackage{graphicx}
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\usepackage{multicol}
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\usepackage{enumitem}
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\usepackage{titlesec}
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\usepackage{tabularx}
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\usepackage[margin=2.0cm,includefoot,footskip=10pt]{geometry}
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\usepackage[british]{babel}
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\renewcommand{\familydefault}{\sfdefault}
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\titleformat{\section}[block]{}{}{0pt}{\normalfont\large\bfseries}
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\pagestyle{empty}
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\setlength{\parindent}{0pt}
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\setlist[itemize]{leftmargin=*,nosep}
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\begin{document}
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\begin{minipage}{0.5\textwidth}
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\raggedright
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\includegraphics[width=0.6\textwidth]{opencores.png}
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\end{minipage}
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\begin{minipage}{0.5\textwidth}
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\raggedleft\Large\bf
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\textsf{The Potato Processor\\Datasheet}
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\end{minipage}
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\vspace{0.5em}
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\noindent\rule{\linewidth}{1pt}\\
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\begin{minipage}[t]{0.48\textwidth}
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\section{Architecture}
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\includegraphics[width=\textwidth]{diagram.png}
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\section{Features}
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\begin{itemize}
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\item Supports the complete 32-bit RISC-V base integer ISA (RV32I) version 2.0
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\item Supports machine mode as defined by the RISC-V supervisor extensions version 1.7
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\item Includes a hardware timer with microsecond resolution and compare interrupt
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\item 8 IRQ inputs that can be invidually enabled
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\item Classic 5-stage RISC pipeline
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\item Instruction cache
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\item Wishbone interface
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\item Automatic test suite
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\end{itemize}
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\section{Interface}
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The processor includes a wishbone interface conforming to the B4 revision of the
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wishbone specification.\\
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\begin{tabularx}{\textwidth}{|l|X|}
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\hline
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Interface type & Master \\
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Address port width & 32 bits \\
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Data port width & 32 bits \\
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Data port granularity & 8 bits \\
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Maximum operand size & 32 bits \\
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Endianess & Little \\
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Sequence of data transfer & In-order \\
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\hline
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\end{tabularx}
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\section{Programming}
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Tools for writing programmes for the RISC-V architecture are available from the
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RISC-V project, at:\\[1em]
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\url{https://github.com/riscv/riscv-tools}\\
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Use the \texttt{new\_privileged\_isa} branch to get tools that work with the
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current supervisor extensions.
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\end{minipage}\hfill
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\begin{minipage}[t]{0.48\textwidth}
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\section{Application}
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\includegraphics[width=\textwidth]{example.png}
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\section{Signals}
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The processor is provided by a VHDL module named \texttt{pp\_potato}. The signals of
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the module are all active high and are as follows:\\
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\begin{tabularx}{\textwidth}{|l|l|X|}
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\hline
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\textbf{Name} & \textbf{Width} & \textbf{Description} \\
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\hline
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\texttt{clk} & 1 & Processor clock \\
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\texttt{timer\_clk} & 1 & 10~MHz timer clock \\
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\texttt{reset} & 1 & Reset signal \\
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\hline
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\texttt{irq} & 8 & IRQ inputs \\
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\hline
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\texttt{wb\_adr\_out} & 32 & Wishbone address \\
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\texttt{wb\_sel\_out} & 4 & Wishbone byte select \\
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\texttt{wb\_cyc\_out} & 1 & Wishbone cycle \\
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\texttt{wb\_stb\_out} & 1 & Wishbone strobe \\
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\texttt{wb\_we\_out} & 1 & Wishbone write enable \\
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\texttt{wb\_dat\_out} & 32 & Wishbone data output \\
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\texttt{wb\_dat\_in} & 32 & Wishbone data input \\
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\texttt{wb\_ack\_in} & 1 & Wishbone acknowledge \\
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\hline
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\end{tabularx}\\
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Additional signals are used to implement a host-target interface used in the automatic testing
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environment. These signals have names starting with \texttt{fromhost} and \texttt{tohost} and
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should be left unconnected for normal use.\\
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\section{Specifications}
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The base RISC-V instruction set and the privileged extensions are available in the
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specifications published at:\\
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\url{http://riscv.org/download.html}.
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\end{minipage}
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\vfill
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\noindent\rule{\linewidth}{1pt}
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{\small
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Project page: \url{http://opencores.org/project,potato}\\
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Report bugs and issues on \url{http://opencores.org/project,potato,bugtracker}}
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\end{document}
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