URL
https://opencores.org/ocsvn/potato/potato/trunk
[/] [potato/] [trunk/] [example/] [README] - Blame information for rev 10
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
7 |
skordal |
# Demo design for the Nexys 4 board
|
2 |
|
|
|
3 |
|
|
This folder contains a design for a simple demo design using the Potato
|
4 |
|
|
processor. It has been tested using Vivado 2014.4.
|
5 |
|
|
|
6 |
|
|
## Quick Start
|
7 |
|
|
|
8 |
|
|
In order to use the design, first import all source files from the folders
|
9 |
|
|
`src/`, `soc/` and `example/` into your project.
|
10 |
|
|
|
11 |
|
|
### Clocking
|
12 |
|
|
|
13 |
|
|
Then add a clock generator using the Clocking Wizard. To seamlessly integrate
|
14 |
|
|
it into the design, name it "clock_generator". Choose the following options:
|
15 |
|
|
|
16 |
|
|
* Frequency Synthesis
|
17 |
|
|
* Safe Clock Startup
|
18 |
|
|
|
19 |
|
|
Set up two output clocks, `clk_out1` with frequency 50 MHz, and `clk_out2` with
|
20 |
|
|
a frequency of 10 MHz. Rename the corresponding ports to `system_clk` and
|
21 |
|
|
`timer_clk` respectively. Name the input clock `clk`.
|
22 |
|
|
|
23 |
|
|
### Instruction memory
|
24 |
|
|
|
25 |
|
|
Add a block RAM to use as instruction ROM using the Block Memory Generator.
|
26 |
8 |
skordal |
Choose "Single Port ROM" as memory type, name it "instruction_rom" and set
|
27 |
|
|
port A width to 32 bits and port A depth to 2048. Initialize it with your
|
28 |
|
|
application binary and, optionally, fill the remaining memory locations with
|
29 |
|
|
0x00000013.
|
30 |
7 |
skordal |
|
31 |
|
|
### Test it!
|
32 |
|
|
|
33 |
|
|
Now you can test it and hopefully it works :-)
|
34 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.