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[/] [potato/] [trunk/] [example/] [tb_toplevel.vhd] - Blame information for rev 12

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1 12 skordal
-- Practical Test Application for the Potato Processor
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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use ieee.std_logic_1164.all;
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entity tb_toplevel is
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end entity tb_toplevel;
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architecture testbench of tb_toplevel is
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        signal clk : std_logic;
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        constant clk_period : time := 10 ns;
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        signal reset_n            : std_logic := '0';
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        signal external_interrupt : std_logic := '0';
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        signal switches : std_logic_vector(15 downto 0);
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        signal leds : std_logic_vector(15 downto 0);
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        signal uart_rxd : std_logic := '1';
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        signal uart_txd : std_logic;
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begin
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        switches <= x"a0a0";
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        uut: entity work.toplevel
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                port map(
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                        clk => clk,
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                        reset_n => reset_n,
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                        external_interrupt => external_interrupt,
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                        switches => switches,
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                        leds => leds,
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                        uart_rxd => uart_rxd,
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                        uart_txd => uart_txd
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                );
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        clock: process
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        begin
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                clk <= '0';
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                wait for clk_period / 2;
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                clk <= '1';
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                wait for clk_period / 2;
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        end process clock;
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        stimulus: process
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        begin
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                wait for clk_period * 125;
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                reset_n <= '0';
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                wait for clk_period * 3;
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                reset_n <= '1';
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                wait;
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        end process stimulus;
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end architecture testbench;

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