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[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Blame information for rev 44

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-- Practical Test Application for the Potato Processor
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
 
entity toplevel is
        port(
                clk       : in std_logic; -- System clock, 100 MHz
                reset_n   : in std_logic; -- CPU reset signal, active low
 
                -- External interrupt input:
                external_interrupt : in std_logic;
 
                -- GPIO pins, must be inout to use with the GPIO module:
                switches : inout std_logic_vector(15 downto 0);
                leds     : inout std_logic_vector(15 downto 0);
 
                -- UART1 (host) pins:
                uart_txd : out std_logic;
                uart_rxd : in  std_logic
        );
end entity toplevel;
 
architecture behaviour of toplevel is
        signal system_clk : std_logic;
        signal timer_clk : std_logic;
 
        -- Active high reset signal:
        signal reset : std_logic;
 
        -- IRQs:
        signal irq   : std_logic_vector(7 downto 0);
        signal uart_irq_rts, uart_irq_recv : std_logic;
        signal timer_irq : std_logic;
 
        -- Processor wishbone interface:
        signal p_adr_out : std_logic_vector(31 downto 0);
        signal p_dat_out : std_logic_vector(31 downto 0);
        signal p_dat_in  : std_logic_vector(31 downto 0);
        signal p_sel_out : std_logic_vector( 3 downto 0);
        signal p_we_out  : std_logic;
        signal p_cyc_out, p_stb_out : std_logic;
        signal p_ack_in  : std_logic;
 
        -- Instruction memory wishbone interface:
        signal imem_adr_in  : std_logic_vector(12 downto 0);
        signal imem_dat_out : std_logic_vector(31 downto 0);
        signal imem_cyc_in, imem_stb_in : std_logic;
        signal imem_ack_out : std_logic;
 
        -- Data memory wishbone interface:
        signal dmem_adr_in  : std_logic_vector(12 downto 0);
        signal dmem_dat_in  : std_logic_vector(31 downto 0);
        signal dmem_dat_out : std_logic_vector(31 downto 0);
        signal dmem_sel_in  : std_logic_vector( 3 downto 0);
        signal dmem_we_in   : std_logic;
        signal dmem_cyc_in, dmem_stb_in : std_logic;
        signal dmem_ack_out : std_logic;
 
        -- GPIO module I (switches) wishbone interface:
        signal gpio1_adr_in  : std_logic_vector(1 downto 0);
        signal gpio1_dat_in  : std_logic_vector(31 downto 0);
        signal gpio1_dat_out : std_logic_vector(31 downto 0);
        signal gpio1_we_in   : std_logic;
        signal gpio1_cyc_in, gpio1_stb_in : std_logic;
        signal gpio1_ack_out : std_logic;
 
        -- GPIO module II (LEDs) wishbone interface:
        signal gpio2_adr_in  : std_logic_vector(1 downto 0);
        signal gpio2_dat_in  : std_logic_vector(31 downto 0);
        signal gpio2_dat_out : std_logic_vector(31 downto 0);
        signal gpio2_we_in   : std_logic;
        signal gpio2_cyc_in, gpio2_stb_in : std_logic;
        signal gpio2_ack_out : std_logic;
 
        -- UART module wishbone interface:
        signal uart_adr_in  : std_logic_vector(1 downto 0);
        signal uart_dat_in  : std_logic_vector(7 downto 0);
        signal uart_dat_out : std_logic_vector(7 downto 0);
        signal uart_we_in   : std_logic;
        signal uart_cyc_in, uart_stb_in : std_logic;
        signal uart_ack_out : std_logic;
 
        -- Timer module wishbone interface:
        signal timer_adr_in  : std_logic_vector(1 downto 0);
        signal timer_dat_in  : std_logic_vector(31 downto 0);
        signal timer_dat_out : std_logic_vector(31 downto 0);
        signal timer_we_in   : std_logic;
        signal timer_cyc_in, timer_stb_in : std_logic;
        signal timer_ack_out : std_logic;
 
        -- Dummy module interface:
        signal dummy_dat_in  : std_logic_vector(31 downto 0);
        signal dummy_dat_out : std_logic_vector(31 downto 0);
        signal dummy_we_in   : std_logic;
        signal dummy_cyc_in, dummy_stb_in : std_logic;
        signal dummy_ack_out : std_logic;
 
        -- Address decoder signals:
        type ad_state_type is (IDLE, BUSY);
        signal ad_state : ad_state_type;
 
        type module_name is (
                        MODULE_IMEM, MODULE_DMEM,       -- Memory modules
                        MODULE_GPIO1, MODULE_GPIO2,     -- GPIO modules
                        MODULE_UART,    -- UART module
                        MODULE_TIMER,   -- Timer module
                        MODULE_DUMMY,   -- Dummy module, used for invalid addresses
                        MODULE_NONE             -- Boring no-module mode
                );
        signal active_module : module_name;
 
begin
 
        reset <= not reset_n;
        irq <= (
 
                        1 => uart_irq_rts, 2 => uart_irq_recv,
                        5 => timer_irq, others => '0'
                );
 
        clkgen: entity work.clock_generator
                port map(
                        clk => clk,
                        system_clk => system_clk,
                        timer_clk => timer_clk
                );
 
        processor: entity work.pp_potato
                port map(
                        clk => system_clk,
                        reset => reset,
                        irq => irq,
                        fromhost_data => (others => '0'),
                        fromhost_updated => '0',
                        tohost_data => open,
                        tohost_updated => open,
                        wb_adr_out => p_adr_out,
                        wb_dat_out => p_dat_out,
                        wb_dat_in => p_dat_in,
                        wb_sel_out => p_sel_out,
                        wb_we_out => p_we_out,
                        wb_cyc_out => p_cyc_out,
                        wb_stb_out => p_stb_out,
                        wb_ack_in => p_ack_in
                );
 
        imem: entity work.imem_wrapper
                port map(
                        clk => system_clk,
                        reset => reset,
                        wb_adr_in => imem_adr_in,
                        wb_dat_out => imem_dat_out,
                        wb_cyc_in => imem_cyc_in,
                        wb_stb_in => imem_stb_in,
                        wb_ack_out => imem_ack_out
                );
 
        dmem: entity work.pp_soc_memory
                generic map(
                        MEMORY_SIZE => 8192
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        wb_adr_in => dmem_adr_in,
                        wb_dat_in => dmem_dat_in,
                        wb_dat_out => dmem_dat_out,
                        wb_sel_in => dmem_sel_in,
                        wb_we_in => dmem_we_in,
                        wb_cyc_in => dmem_cyc_in,
                        wb_stb_in => dmem_stb_in,
                        wb_ack_out => dmem_ack_out
                );
 
        gpio1: entity work.pp_soc_gpio
                generic map(
                        NUM_GPIOS => 16
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        gpio => switches,
                        wb_adr_in => gpio1_adr_in,
                        wb_dat_in => gpio1_dat_in,
                        wb_dat_out => gpio1_dat_out,
                        wb_cyc_in => gpio1_cyc_in,
                        wb_stb_in => gpio1_stb_in,
                        wb_we_in => gpio1_we_in,
                        wb_ack_out => gpio1_ack_out
                );
 
        gpio2: entity work.pp_soc_gpio
                generic map(
                        NUM_GPIOS => 16
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        gpio => leds,
                        wb_adr_in => gpio2_adr_in,
                        wb_dat_in => gpio2_dat_in,
                        wb_dat_out => gpio2_dat_out,
                        wb_cyc_in => gpio2_cyc_in,
                        wb_stb_in => gpio2_stb_in,
                        wb_we_in => gpio2_we_in,
                        wb_ack_out => gpio2_ack_out
                );
 
        uart1: entity work.pp_soc_uart
                generic map(
                        FIFO_DEPTH => 64,
                        --SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
                        SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        txd => uart_txd,
                        rxd => uart_rxd,
                        irq_send_buffer_empty => uart_irq_rts,
                        irq_data_received => uart_irq_recv,
                        wb_adr_in => uart_adr_in,
                        wb_dat_in => uart_dat_in,
                        wb_dat_out => uart_dat_out,
                        wb_cyc_in => uart_cyc_in,
                        wb_stb_in => uart_stb_in,
                        wb_we_in => uart_we_in,
                        wb_ack_out => uart_ack_out
                );
 
        timer1: entity work.pp_soc_timer
                port map(
                        clk => system_clk,
                        reset => reset,
                        irq => timer_irq,
                        wb_adr_in => timer_adr_in,
                        wb_dat_in => timer_dat_in,
                        wb_dat_out => timer_dat_out,
                        wb_cyc_in => timer_cyc_in,
                        wb_stb_in => timer_stb_in,
                        wb_we_in => timer_we_in,
                        wb_ack_out => timer_ack_out
                );
 
        dummy: entity work.pp_soc_dummy
                port map(
                        clk => system_clk,
                        reset => reset,
                        wb_dat_in => dummy_dat_in,
                        wb_dat_out => dummy_dat_out,
                        wb_cyc_in => dummy_cyc_in,
                        wb_stb_in => dummy_stb_in,
                        wb_we_in => dummy_we_in,
                        wb_ack_out => dummy_ack_out
                );
 
        imem_cyc_in <= p_cyc_out when active_module = MODULE_IMEM else '0';
        dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';
        gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';
        gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';
        uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';
        timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';
        dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';
 
        imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';
        dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';
        gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';
        gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';
        uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';
        timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';
        dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';
 
        imem_adr_in <= p_adr_out(12 downto 0);
        dmem_adr_in <= p_adr_out(12 downto 0);
        gpio1_adr_in <= p_adr_out(3 downto 2);
        gpio2_adr_in <= p_adr_out(3 downto 2);
        uart_adr_in <=  p_adr_out(3 downto 2);
        timer_adr_in <= p_adr_out(3 downto 2);
 
        dmem_dat_in <= p_dat_out;
        gpio1_dat_in <= p_dat_out;
        gpio2_dat_in <= p_dat_out;
        uart_dat_in <= p_dat_out(7 downto 0);
        timer_dat_in <= p_dat_out;
        dummy_dat_in <= p_dat_out;
 
        dmem_sel_in <= p_sel_out;
 
        gpio1_we_in <= p_we_out;
        gpio2_we_in <= p_we_out;
        dmem_we_in <= p_we_out;
        uart_we_in <= p_we_out;
        timer_we_in <= p_we_out;
        dummy_we_in <= p_we_out;
 
        address_decoder: process(system_clk)
        begin
                if rising_edge(system_clk) then
                        if reset = '1' then
                                ad_state <= IDLE;
                                active_module <= MODULE_NONE;
                        else
                                case ad_state is
                                        when IDLE =>
                                                if p_cyc_out = '1' and p_stb_out = '1' then
                                                        if p_adr_out(31 downto 13) = b"0000000000000000000" then
                                                                active_module <= MODULE_IMEM;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000
                                                                active_module <= MODULE_DMEM;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001000" then -- 0x4000
                                                                active_module <= MODULE_GPIO1;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001001" then -- 0x4800
                                                                active_module <= MODULE_GPIO2;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001010" then -- 0x5000
                                                                active_module <= MODULE_UART;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800
                                                                active_module <= MODULE_TIMER;
                                                                ad_state <= BUSY;
                                                        else
                                                                active_module <= MODULE_DUMMY;
                                                                ad_state <= BUSY;
                                                        end if;
                                                end if;
                                        when BUSY =>
                                                if p_cyc_out = '0' then
                                                        active_module <= MODULE_NONE;
                                                        ad_state <= IDLE;
                                                end if;
                                end case;
                        end if;
                end if;
        end process address_decoder;
 
        module_mux: process(active_module, imem_ack_out, imem_dat_out, dmem_ack_out, dmem_dat_out,
                gpio1_ack_out, gpio1_dat_out, gpio2_ack_out, gpio2_dat_out, uart_ack_out, uart_dat_out,
                timer_ack_out, timer_dat_out, dummy_ack_out, dummy_dat_out)
        begin
                case active_module is
                        when MODULE_IMEM =>
                                p_ack_in <= imem_ack_out;
                                p_dat_in <= imem_dat_out;
                        when MODULE_DMEM =>
                                p_ack_in <= dmem_ack_out;
                                p_dat_in <= dmem_dat_out;
                        when MODULE_GPIO1 =>
                                p_ack_in <= gpio1_ack_out;
                                p_dat_in <= gpio1_dat_out;
                        when MODULE_GPIO2 =>
                                p_ack_in <= gpio2_ack_out;
                                p_dat_in <= gpio2_dat_out;
                        when MODULE_UART =>
                                p_ack_in <= uart_ack_out;
                                p_dat_in <= (31 downto 8 => '0') & uart_dat_out;
                        when MODULE_TIMER =>
                                p_ack_in <= timer_ack_out;
                                p_dat_in <= timer_dat_out;
                        when MODULE_DUMMY =>
                                p_ack_in <= dummy_ack_out;
                                p_dat_in <= dummy_dat_out;
                        when MODULE_NONE =>
                                p_ack_in <= '0';
                                p_dat_in <= (others => '0');
                end case;
        end process module_mux;
 
end architecture behaviour;

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[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Blame information for rev 44

Line No.	Rev	Author	Line
1	7	skordal	`-- Practical Test Application for the Potato Processor`
2			`-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>`
3	12	skordal	`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4	7	skordal
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7
8			`entity toplevel is`
9			`port(`
10			`clk : in std_logic; -- System clock, 100 MHz`
11			`reset_n : in std_logic; -- CPU reset signal, active low`
12
13			`-- External interrupt input:`
14			`external_interrupt : in std_logic;`
15
16			`-- GPIO pins, must be inout to use with the GPIO module:`
17			`switches : inout std_logic_vector(15 downto 0);`
18			`leds : inout std_logic_vector(15 downto 0);`
19
20			`-- UART1 (host) pins:`
21			`uart_txd : out std_logic;`
22			`uart_rxd : in std_logic`
23			`);`
24			`end entity toplevel;`
25
26			`architecture behaviour of toplevel is`
27			`signal system_clk : std_logic;`
28			`signal timer_clk : std_logic;`
29
30			`-- Active high reset signal:`
31			`signal reset : std_logic;`
32
33			`-- IRQs:`
34			`signal irq : std_logic_vector(7 downto 0);`
35			`signal uart_irq_rts, uart_irq_recv : std_logic;`
36			`signal timer_irq : std_logic;`
37
38			`-- Processor wishbone interface:`
39			`signal p_adr_out : std_logic_vector(31 downto 0);`
40			`signal p_dat_out : std_logic_vector(31 downto 0);`
41			`signal p_dat_in : std_logic_vector(31 downto 0);`
42			`signal p_sel_out : std_logic_vector( 3 downto 0);`
43			`signal p_we_out : std_logic;`
44			`signal p_cyc_out, p_stb_out : std_logic;`
45			`signal p_ack_in : std_logic;`
46
47			`-- Instruction memory wishbone interface:`
48			`signal imem_adr_in : std_logic_vector(12 downto 0);`
49			`signal imem_dat_out : std_logic_vector(31 downto 0);`
50			`signal imem_cyc_in, imem_stb_in : std_logic;`
51			`signal imem_ack_out : std_logic;`
52
53			`-- Data memory wishbone interface:`
54			`signal dmem_adr_in : std_logic_vector(12 downto 0);`
55			`signal dmem_dat_in : std_logic_vector(31 downto 0);`
56			`signal dmem_dat_out : std_logic_vector(31 downto 0);`
57			`signal dmem_sel_in : std_logic_vector( 3 downto 0);`
58			`signal dmem_we_in : std_logic;`
59			`signal dmem_cyc_in, dmem_stb_in : std_logic;`
60			`signal dmem_ack_out : std_logic;`
61
62			`-- GPIO module I (switches) wishbone interface:`
63			`signal gpio1_adr_in : std_logic_vector(1 downto 0);`
64			`signal gpio1_dat_in : std_logic_vector(31 downto 0);`
65			`signal gpio1_dat_out : std_logic_vector(31 downto 0);`
66			`signal gpio1_we_in : std_logic;`
67			`signal gpio1_cyc_in, gpio1_stb_in : std_logic;`
68			`signal gpio1_ack_out : std_logic;`
69
70			`-- GPIO module II (LEDs) wishbone interface:`
71			`signal gpio2_adr_in : std_logic_vector(1 downto 0);`
72			`signal gpio2_dat_in : std_logic_vector(31 downto 0);`
73			`signal gpio2_dat_out : std_logic_vector(31 downto 0);`
74			`signal gpio2_we_in : std_logic;`
75			`signal gpio2_cyc_in, gpio2_stb_in : std_logic;`
76			`signal gpio2_ack_out : std_logic;`
77
78			`-- UART module wishbone interface:`
79			`signal uart_adr_in : std_logic_vector(1 downto 0);`
80			`signal uart_dat_in : std_logic_vector(7 downto 0);`
81			`signal uart_dat_out : std_logic_vector(7 downto 0);`
82			`signal uart_we_in : std_logic;`
83			`signal uart_cyc_in, uart_stb_in : std_logic;`
84			`signal uart_ack_out : std_logic;`
85
86			`-- Timer module wishbone interface:`
87			`signal timer_adr_in : std_logic_vector(1 downto 0);`
88			`signal timer_dat_in : std_logic_vector(31 downto 0);`
89			`signal timer_dat_out : std_logic_vector(31 downto 0);`
90			`signal timer_we_in : std_logic;`
91			`signal timer_cyc_in, timer_stb_in : std_logic;`
92			`signal timer_ack_out : std_logic;`
93
94			`-- Dummy module interface:`
95			`signal dummy_dat_in : std_logic_vector(31 downto 0);`
96			`signal dummy_dat_out : std_logic_vector(31 downto 0);`
97			`signal dummy_we_in : std_logic;`
98			`signal dummy_cyc_in, dummy_stb_in : std_logic;`
99			`signal dummy_ack_out : std_logic;`
100
101			`-- Address decoder signals:`
102			`type ad_state_type is (IDLE, BUSY);`
103			`signal ad_state : ad_state_type;`
104
105			`type module_name is (`
106			`MODULE_IMEM, MODULE_DMEM, -- Memory modules`
107			`MODULE_GPIO1, MODULE_GPIO2, -- GPIO modules`
108			`MODULE_UART, -- UART module`
109			`MODULE_TIMER, -- Timer module`
110			`MODULE_DUMMY, -- Dummy module, used for invalid addresses`
111	21	skordal	`MODULE_NONE -- Boring no-module mode`
112	7	skordal	`);`
113			`signal active_module : module_name;`
114
115			`begin`
116
117			`reset <= not reset_n;`
118			`irq <= (`
119
120			`1 => uart_irq_rts, 2 => uart_irq_recv,`
121			`5 => timer_irq, others => '0'`
122			`);`
123
124			`clkgen: entity work.clock_generator`
125			`port map(`
126			`clk => clk,`
127			`system_clk => system_clk,`
128			`timer_clk => timer_clk`
129			`);`
130
131			`processor: entity work.pp_potato`
132			`port map(`
133			`clk => system_clk,`
134			`reset => reset,`
135			`irq => irq,`
136			`fromhost_data => (others => '0'),`
137			`fromhost_updated => '0',`
138			`tohost_data => open,`
139			`tohost_updated => open,`
140			`wb_adr_out => p_adr_out,`
141			`wb_dat_out => p_dat_out,`
142			`wb_dat_in => p_dat_in,`
143			`wb_sel_out => p_sel_out,`
144			`wb_we_out => p_we_out,`
145			`wb_cyc_out => p_cyc_out,`
146			`wb_stb_out => p_stb_out,`
147			`wb_ack_in => p_ack_in`
148			`);`
149
150			`imem: entity work.imem_wrapper`
151			`port map(`
152			`clk => system_clk,`
153			`reset => reset,`
154			`wb_adr_in => imem_adr_in,`
155			`wb_dat_out => imem_dat_out,`
156			`wb_cyc_in => imem_cyc_in,`
157			`wb_stb_in => imem_stb_in,`
158			`wb_ack_out => imem_ack_out`
159			`);`
160
161			`dmem: entity work.pp_soc_memory`
162			`generic map(`
163			`MEMORY_SIZE => 8192`
164			`) port map(`
165			`clk => system_clk,`
166			`reset => reset,`
167			`wb_adr_in => dmem_adr_in,`
168			`wb_dat_in => dmem_dat_in,`
169			`wb_dat_out => dmem_dat_out,`
170			`wb_sel_in => dmem_sel_in,`
171			`wb_we_in => dmem_we_in,`
172			`wb_cyc_in => dmem_cyc_in,`
173			`wb_stb_in => dmem_stb_in,`
174			`wb_ack_out => dmem_ack_out`
175			`);`
176
177			`gpio1: entity work.pp_soc_gpio`
178			`generic map(`
179			`NUM_GPIOS => 16`
180			`) port map(`
181			`clk => system_clk,`
182			`reset => reset,`
183			`gpio => switches,`
184			`wb_adr_in => gpio1_adr_in,`
185			`wb_dat_in => gpio1_dat_in,`
186			`wb_dat_out => gpio1_dat_out,`
187			`wb_cyc_in => gpio1_cyc_in,`
188			`wb_stb_in => gpio1_stb_in,`
189			`wb_we_in => gpio1_we_in,`
190			`wb_ack_out => gpio1_ack_out`
191			`);`
192
193			`gpio2: entity work.pp_soc_gpio`
194			`generic map(`
195			`NUM_GPIOS => 16`
196			`) port map(`
197			`clk => system_clk,`
198			`reset => reset,`
199			`gpio => leds,`
200			`wb_adr_in => gpio2_adr_in,`
201			`wb_dat_in => gpio2_dat_in,`
202			`wb_dat_out => gpio2_dat_out,`
203			`wb_cyc_in => gpio2_cyc_in,`
204			`wb_stb_in => gpio2_stb_in,`
205			`wb_we_in => gpio2_we_in,`
206			`wb_ack_out => gpio2_ack_out`
207			`);`
208
209			`uart1: entity work.pp_soc_uart`
210			`generic map(`
211			`FIFO_DEPTH => 64,`
212	21	skordal	`--SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz`
213			`SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz`
214	7	skordal	`) port map(`
215			`clk => system_clk,`
216			`reset => reset,`
217			`txd => uart_txd,`
218			`rxd => uart_rxd,`
219			`irq_send_buffer_empty => uart_irq_rts,`
220			`irq_data_received => uart_irq_recv,`
221			`wb_adr_in => uart_adr_in,`
222			`wb_dat_in => uart_dat_in,`
223			`wb_dat_out => uart_dat_out,`
224			`wb_cyc_in => uart_cyc_in,`
225			`wb_stb_in => uart_stb_in,`
226			`wb_we_in => uart_we_in,`
227			`wb_ack_out => uart_ack_out`
228			`);`
229
230			`timer1: entity work.pp_soc_timer`
231			`port map(`
232			`clk => system_clk,`
233			`reset => reset,`
234			`irq => timer_irq,`
235			`wb_adr_in => timer_adr_in,`
236			`wb_dat_in => timer_dat_in,`
237			`wb_dat_out => timer_dat_out,`
238			`wb_cyc_in => timer_cyc_in,`
239			`wb_stb_in => timer_stb_in,`
240			`wb_we_in => timer_we_in,`
241			`wb_ack_out => timer_ack_out`
242			`);`
243
244			`dummy: entity work.pp_soc_dummy`
245			`port map(`
246			`clk => system_clk,`
247			`reset => reset,`
248			`wb_dat_in => dummy_dat_in,`
249			`wb_dat_out => dummy_dat_out,`
250			`wb_cyc_in => dummy_cyc_in,`
251			`wb_stb_in => dummy_stb_in,`
252			`wb_we_in => dummy_we_in,`
253			`wb_ack_out => dummy_ack_out`
254			`);`
255
256			`imem_cyc_in <= p_cyc_out when active_module = MODULE_IMEM else '0';`
257			`dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';`
258			`gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';`
259			`gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';`
260			`uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';`
261			`timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';`
262			`dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';`
263
264			`imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';`
265			`dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';`
266			`gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';`
267			`gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';`
268			`uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';`
269			`timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';`
270			`dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';`
271
272			`imem_adr_in <= p_adr_out(12 downto 0);`
273			`dmem_adr_in <= p_adr_out(12 downto 0);`
274			`gpio1_adr_in <= p_adr_out(3 downto 2);`
275			`gpio2_adr_in <= p_adr_out(3 downto 2);`
276			`uart_adr_in <= p_adr_out(3 downto 2);`
277			`timer_adr_in <= p_adr_out(3 downto 2);`
278
279			`dmem_dat_in <= p_dat_out;`
280			`gpio1_dat_in <= p_dat_out;`
281			`gpio2_dat_in <= p_dat_out;`
282			`uart_dat_in <= p_dat_out(7 downto 0);`
283			`timer_dat_in <= p_dat_out;`
284			`dummy_dat_in <= p_dat_out;`
285
286			`dmem_sel_in <= p_sel_out;`
287
288			`gpio1_we_in <= p_we_out;`
289			`gpio2_we_in <= p_we_out;`
290			`dmem_we_in <= p_we_out;`
291			`uart_we_in <= p_we_out;`
292			`timer_we_in <= p_we_out;`
293			`dummy_we_in <= p_we_out;`
294
295			`address_decoder: process(system_clk)`
296			`begin`
297			`if rising_edge(system_clk) then`
298			`if reset = '1' then`
299			`ad_state <= IDLE;`
300			`active_module <= MODULE_NONE;`
301			`else`
302			`case ad_state is`
303			`when IDLE =>`
304			`if p_cyc_out = '1' and p_stb_out = '1' then`
305			`if p_adr_out(31 downto 13) = b"0000000000000000000" then`
306			`active_module <= MODULE_IMEM;`
307			`ad_state <= BUSY;`
308			`elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000`
309			`active_module <= MODULE_DMEM;`
310			`ad_state <= BUSY;`
311			`elsif p_adr_out(31 downto 11) = b"000000000000000001000" then -- 0x4000`
312			`active_module <= MODULE_GPIO1;`
313			`ad_state <= BUSY;`
314			`elsif p_adr_out(31 downto 11) = b"000000000000000001001" then -- 0x4800`
315			`active_module <= MODULE_GPIO2;`
316			`ad_state <= BUSY;`
317			`elsif p_adr_out(31 downto 11) = b"000000000000000001010" then -- 0x5000`
318			`active_module <= MODULE_UART;`
319			`ad_state <= BUSY;`
320			`elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800`
321			`active_module <= MODULE_TIMER;`
322			`ad_state <= BUSY;`
323			`else`
324			`active_module <= MODULE_DUMMY;`
325			`ad_state <= BUSY;`
326			`end if;`
327			`end if;`
328			`when BUSY =>`
329			`if p_cyc_out = '0' then`
330			`active_module <= MODULE_NONE;`
331			`ad_state <= IDLE;`
332			`end if;`
333			`end case;`
334			`end if;`
335			`end if;`
336			`end process address_decoder;`
337
338			`module_mux: process(active_module, imem_ack_out, imem_dat_out, dmem_ack_out, dmem_dat_out,`
339			`gpio1_ack_out, gpio1_dat_out, gpio2_ack_out, gpio2_dat_out, uart_ack_out, uart_dat_out,`
340			`timer_ack_out, timer_dat_out, dummy_ack_out, dummy_dat_out)`
341			`begin`
342			`case active_module is`
343			`when MODULE_IMEM =>`
344			`p_ack_in <= imem_ack_out;`
345			`p_dat_in <= imem_dat_out;`
346			`when MODULE_DMEM =>`
347			`p_ack_in <= dmem_ack_out;`
348			`p_dat_in <= dmem_dat_out;`
349			`when MODULE_GPIO1 =>`
350			`p_ack_in <= gpio1_ack_out;`
351			`p_dat_in <= gpio1_dat_out;`
352			`when MODULE_GPIO2 =>`
353			`p_ack_in <= gpio2_ack_out;`
354			`p_dat_in <= gpio2_dat_out;`
355			`when MODULE_UART =>`
356			`p_ack_in <= uart_ack_out;`
357			`p_dat_in <= (31 downto 8 => '0') & uart_dat_out;`
358			`when MODULE_TIMER =>`
359			`p_ack_in <= timer_ack_out;`
360			`p_dat_in <= timer_dat_out;`
361			`when MODULE_DUMMY =>`
362			`p_ack_in <= dummy_ack_out;`
363			`p_dat_in <= dummy_dat_out;`
364			`when MODULE_NONE =>`
365			`p_ack_in <= '0';`
366			`p_dat_in <= (others => '0');`
367			`end case;`
368			`end process module_mux;`
369
370			`end architecture behaviour;`