URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Blame information for rev 61

Go to most recent revision | Details | Compare with Previous | View Log


-- Practical Test Application for the Potato Processor
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
 
entity toplevel is
        port(
                clk       : in std_logic; -- External clock input, 100 MHz
                reset_n   : in std_logic; -- CPU reset signal, active low
 
                -- External interrupt input:
                external_interrupt : in std_logic;
 
                -- GPIO pins, must be inout to use with the GPIO module:
                switches : inout std_logic_vector(15 downto 0);
                leds     : inout std_logic_vector(15 downto 0);
 
                -- UART pins:
                uart_txd : out std_logic;
                uart_rxd : in  std_logic;
 
                -- 7-Segment display pins:
                seg7_anode   : out std_logic_vector(7 downto 0);
                seg7_cathode : out std_logic_vector(6 downto 0)
        );
end entity toplevel;
 
architecture behaviour of toplevel is
        signal system_clk : std_logic;
        signal timer_clk : std_logic;
 
        -- Active high reset signal:
        signal reset : std_logic;
 
        -- IRQs:
        signal irq   : std_logic_vector(7 downto 0);
        signal uart_irq_rts, uart_irq_recv : std_logic;
        signal timer_irq : std_logic;
 
        -- Processor wishbone interface:
        signal p_adr_out : std_logic_vector(31 downto 0);
        signal p_dat_out : std_logic_vector(31 downto 0);
        signal p_dat_in  : std_logic_vector(31 downto 0);
        signal p_sel_out : std_logic_vector( 3 downto 0);
        signal p_we_out  : std_logic;
        signal p_cyc_out, p_stb_out : std_logic;
        signal p_ack_in  : std_logic;
 
        -- Instruction memory wishbone interface:
        signal imem_adr_in  : std_logic_vector(12 downto 0);
        signal imem_dat_out : std_logic_vector(31 downto 0);
        signal imem_cyc_in, imem_stb_in : std_logic;
        signal imem_ack_out : std_logic;
 
        -- Data memory wishbone interface:
        signal dmem_adr_in  : std_logic_vector(12 downto 0);
        signal dmem_dat_in  : std_logic_vector(31 downto 0);
        signal dmem_dat_out : std_logic_vector(31 downto 0);
        signal dmem_sel_in  : std_logic_vector( 3 downto 0);
        signal dmem_we_in   : std_logic;
        signal dmem_cyc_in, dmem_stb_in : std_logic;
        signal dmem_ack_out : std_logic;
 
        -- GPIO module I (switches) wishbone interface:
        signal gpio1_adr_in  : std_logic_vector( 1 downto 0);
        signal gpio1_dat_in  : std_logic_vector(31 downto 0);
        signal gpio1_dat_out : std_logic_vector(31 downto 0);
        signal gpio1_we_in   : std_logic;
        signal gpio1_cyc_in, gpio1_stb_in : std_logic;
        signal gpio1_ack_out : std_logic;
 
        -- GPIO module II (LEDs) wishbone interface:
        signal gpio2_adr_in  : std_logic_vector( 1 downto 0);
        signal gpio2_dat_in  : std_logic_vector(31 downto 0);
        signal gpio2_dat_out : std_logic_vector(31 downto 0);
        signal gpio2_we_in   : std_logic;
        signal gpio2_cyc_in, gpio2_stb_in : std_logic;
        signal gpio2_ack_out : std_logic;
 
        -- UART module wishbone interface:
        signal uart_adr_in  : std_logic_vector(1 downto 0);
        signal uart_dat_in  : std_logic_vector(7 downto 0);
        signal uart_dat_out : std_logic_vector(7 downto 0);
        signal uart_we_in   : std_logic;
        signal uart_cyc_in, uart_stb_in : std_logic;
        signal uart_ack_out : std_logic;
 
        -- Timer module wishbone interface:
        signal timer_adr_in  : std_logic_vector( 1 downto 0);
        signal timer_dat_in  : std_logic_vector(31 downto 0);
        signal timer_dat_out : std_logic_vector(31 downto 0);
        signal timer_we_in   : std_logic;
        signal timer_cyc_in, timer_stb_in : std_logic;
        signal timer_ack_out : std_logic;
 
        -- 7-Segment module wishbone interface:
        signal seg7_adr_in  : std_logic_vector( 0 downto 0);
        signal seg7_dat_in  : std_logic_vector(31 downto 0);
        signal seg7_dat_out : std_logic_vector(31 downto 0);
        signal seg7_we_in   : std_logic;
        signal seg7_cyc_in, seg7_stb_in : std_logic;
        signal seg7_ack_out : std_logic;
 
        -- Dummy module interface:
        signal dummy_dat_in  : std_logic_vector(31 downto 0);
        signal dummy_dat_out : std_logic_vector(31 downto 0);
        signal dummy_we_in   : std_logic;
        signal dummy_cyc_in, dummy_stb_in : std_logic;
        signal dummy_ack_out : std_logic;
 
        -- Address decoder signals:
        type ad_state_type is (IDLE, BUSY);
        signal ad_state : ad_state_type;
 
        type module_name is (
                        MODULE_IMEM, MODULE_DMEM,       -- Memory modules
                        MODULE_GPIO1, MODULE_GPIO2,     -- GPIO modules
                        MODULE_UART,    -- UART module
                        MODULE_TIMER,   -- Timer module
                        MODULE_7SEG,    -- 7-Segment module
                        MODULE_DUMMY,   -- Dummy module, used for invalid addresses
                        MODULE_NONE             -- Boring no-module mode
                );
        signal active_module : module_name;
 
begin
 
        reset <= not reset_n;
        irq <= (
 
                        1 => uart_irq_rts, 2 => uart_irq_recv,
                        5 => timer_irq, others => '0'
                );
 
        clkgen: entity work.clock_generator
                port map(
                        clk => clk,
                        system_clk => system_clk,
                        timer_clk => timer_clk
                );
 
        processor: entity work.pp_potato
                port map(
                        clk => system_clk,
                        timer_clk => timer_clk,
                        reset => reset,
                        irq => irq,
                        fromhost_data => (others => '0'),
                        fromhost_updated => '0',
                        tohost_data => open,
                        tohost_updated => open,
                        wb_adr_out => p_adr_out,
                        wb_dat_out => p_dat_out,
                        wb_dat_in => p_dat_in,
                        wb_sel_out => p_sel_out,
                        wb_we_out => p_we_out,
                        wb_cyc_out => p_cyc_out,
                        wb_stb_out => p_stb_out,
                        wb_ack_in => p_ack_in
                );
 
        imem: entity work.imem_wrapper
                port map(
                        clk => system_clk,
                        reset => reset,
                        wb_adr_in => imem_adr_in,
                        wb_dat_out => imem_dat_out,
                        wb_cyc_in => imem_cyc_in,
                        wb_stb_in => imem_stb_in,
                        wb_ack_out => imem_ack_out
                );
 
        dmem: entity work.pp_soc_memory
                generic map(
                        MEMORY_SIZE => 8192
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        wb_adr_in => dmem_adr_in,
                        wb_dat_in => dmem_dat_in,
                        wb_dat_out => dmem_dat_out,
                        wb_sel_in => dmem_sel_in,
                        wb_we_in => dmem_we_in,
                        wb_cyc_in => dmem_cyc_in,
                        wb_stb_in => dmem_stb_in,
                        wb_ack_out => dmem_ack_out
                );
 
        gpio1: entity work.pp_soc_gpio
                generic map(
                        NUM_GPIOS => 16
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        gpio => switches,
                        wb_adr_in => gpio1_adr_in,
                        wb_dat_in => gpio1_dat_in,
                        wb_dat_out => gpio1_dat_out,
                        wb_cyc_in => gpio1_cyc_in,
                        wb_stb_in => gpio1_stb_in,
                        wb_we_in => gpio1_we_in,
                        wb_ack_out => gpio1_ack_out
                );
 
        gpio2: entity work.pp_soc_gpio
                generic map(
                        NUM_GPIOS => 16
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        gpio => leds,
                        wb_adr_in => gpio2_adr_in,
                        wb_dat_in => gpio2_dat_in,
                        wb_dat_out => gpio2_dat_out,
                        wb_cyc_in => gpio2_cyc_in,
                        wb_stb_in => gpio2_stb_in,
                        wb_we_in => gpio2_we_in,
                        wb_ack_out => gpio2_ack_out
                );
 
        uart1: entity work.pp_soc_uart
                generic map(
                        FIFO_DEPTH => 64,
                        SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
                        --SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        txd => uart_txd,
                        rxd => uart_rxd,
                        irq_send_buffer_empty => uart_irq_rts,
                        irq_data_received => uart_irq_recv,
                        wb_adr_in => uart_adr_in,
                        wb_dat_in => uart_dat_in,
                        wb_dat_out => uart_dat_out,
                        wb_cyc_in => uart_cyc_in,
                        wb_stb_in => uart_stb_in,
                        wb_we_in => uart_we_in,
                        wb_ack_out => uart_ack_out
                );
 
        timer1: entity work.pp_soc_timer
                port map(
                        clk => system_clk,
                        reset => reset,
                        irq => timer_irq,
                        wb_adr_in => timer_adr_in,
                        wb_dat_in => timer_dat_in,
                        wb_dat_out => timer_dat_out,
                        wb_cyc_in => timer_cyc_in,
                        wb_stb_in => timer_stb_in,
                        wb_we_in => timer_we_in,
                        wb_ack_out => timer_ack_out
                );
 
        seg7_1: entity work.pp_soc_7seg
                generic map(
                        SWITCH_COUNT => 50000 -- For 50 MHz
                ) port map(
                        clk => system_clk,
                        reset => reset,
                        seg7_anode => seg7_anode,
                        seg7_cathode => seg7_cathode,
                        wb_adr_in => seg7_adr_in,
                        wb_dat_in => seg7_dat_in,
                        wb_dat_out => seg7_dat_out,
                        wb_cyc_in => seg7_cyc_in,
                        wb_stb_in => seg7_stb_in,
                        wb_we_in => seg7_we_in,
                        wb_ack_out => seg7_ack_out
                );
 
        dummy: entity work.pp_soc_dummy
                port map(
                        clk => system_clk,
                        reset => reset,
                        wb_dat_in => dummy_dat_in,
                        wb_dat_out => dummy_dat_out,
                        wb_cyc_in => dummy_cyc_in,
                        wb_stb_in => dummy_stb_in,
                        wb_we_in => dummy_we_in,
                        wb_ack_out => dummy_ack_out
                );
 
        imem_cyc_in <= p_cyc_out when active_module = MODULE_IMEM else '0';
        dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';
        gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';
        gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';
        uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';
        timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';
        seg7_cyc_in <= p_cyc_out when active_module = MODULE_7SEG else '0';
        dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';
 
        imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';
        dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';
        gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';
        gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';
        uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';
        timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';
        seg7_stb_in <= p_stb_out when active_module = MODULE_7SEG else '0';
        dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';
 
        imem_adr_in <= p_adr_out(12 downto 0);
        dmem_adr_in <= p_adr_out(12 downto 0);
        gpio1_adr_in <= p_adr_out(3 downto 2);
        gpio2_adr_in <= p_adr_out(3 downto 2);
        uart_adr_in <=  p_adr_out(3 downto 2);
        timer_adr_in <= p_adr_out(3 downto 2);
        seg7_adr_in <=  p_adr_out(2 downto 2);
 
        dmem_dat_in <= p_dat_out;
        gpio1_dat_in <= p_dat_out;
        gpio2_dat_in <= p_dat_out;
        uart_dat_in <= p_dat_out(7 downto 0);
        timer_dat_in <= p_dat_out;
        seg7_dat_in <= p_dat_out;
        dummy_dat_in <= p_dat_out;
 
        dmem_sel_in <= p_sel_out;
 
        gpio1_we_in <= p_we_out;
        gpio2_we_in <= p_we_out;
        dmem_we_in <= p_we_out;
        uart_we_in <= p_we_out;
        timer_we_in <= p_we_out;
        seg7_we_in <= p_we_out;
        dummy_we_in <= p_we_out;
 
        address_decoder: process(system_clk)
        begin
                if rising_edge(system_clk) then
                        if reset = '1' then
                                ad_state <= IDLE;
                                active_module <= MODULE_NONE;
                        else
                                case ad_state is
                                        when IDLE =>
                                                if p_cyc_out = '1' then
                                                        if p_adr_out(31 downto 13) = b"0000000000000000000" then
                                                                active_module <= MODULE_IMEM;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000
                                                                active_module <= MODULE_DMEM;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001000" then -- 0x4000
                                                                active_module <= MODULE_GPIO1;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001001" then -- 0x4800
                                                                active_module <= MODULE_GPIO2;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001010" then -- 0x5000
                                                                active_module <= MODULE_UART;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800
                                                                active_module <= MODULE_TIMER;
                                                                ad_state <= BUSY;
                                                        elsif p_adr_out(31 downto 11) = b"000000000000000001100" then -- 0x6000
                                                                active_module <= MODULE_7SEG;
                                                                ad_state <= BUSY;
                                                        else
                                                                active_module <= MODULE_DUMMY;
                                                                ad_state <= BUSY;
                                                        end if;
                                                else
                                                        active_module <= MODULE_NONE;
                                                end if;
                                        when BUSY =>
                                                if p_cyc_out = '0' then
                                                        active_module <= MODULE_NONE;
                                                        ad_state <= IDLE;
                                                end if;
                                end case;
                        end if;
                end if;
        end process address_decoder;
 
        module_mux: process(active_module, imem_ack_out, imem_dat_out, dmem_ack_out, dmem_dat_out,
                gpio1_ack_out, gpio1_dat_out, gpio2_ack_out, gpio2_dat_out, uart_ack_out, uart_dat_out,
                timer_ack_out, timer_dat_out, dummy_ack_out, dummy_dat_out)
        begin
                case active_module is
                        when MODULE_IMEM =>
                                p_ack_in <= imem_ack_out;
                                p_dat_in <= imem_dat_out;
                        when MODULE_DMEM =>
                                p_ack_in <= dmem_ack_out;
                                p_dat_in <= dmem_dat_out;
                        when MODULE_GPIO1 =>
                                p_ack_in <= gpio1_ack_out;
                                p_dat_in <= gpio1_dat_out;
                        when MODULE_GPIO2 =>
                                p_ack_in <= gpio2_ack_out;
                                p_dat_in <= gpio2_dat_out;
                        when MODULE_UART =>
                                p_ack_in <= uart_ack_out;
                                p_dat_in <= (31 downto 8 => '0') & uart_dat_out;
                        when MODULE_TIMER =>
                                p_ack_in <= timer_ack_out;
                                p_dat_in <= timer_dat_out;
                        when MODULE_7SEG =>
                                p_ack_in <= seg7_ack_out;
                                p_dat_in <= seg7_dat_out;
                        when MODULE_DUMMY =>
                                p_ack_in <= dummy_ack_out;
                                p_dat_in <= dummy_dat_out;
                        when MODULE_NONE =>
                                p_ack_in <= '0';
                                p_dat_in <= (others => '0');
                end case;
        end process module_mux;
 
end architecture behaviour;

Line No.	Rev	Author	Line
1	7	skordal	`-- Practical Test Application for the Potato Processor`
2			`-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>`
3	12	skordal	`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4	7	skordal
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7
8			`entity toplevel is`
9			`port(`
10	61	skordal	`clk : in std_logic; -- External clock input, 100 MHz`
11	7	skordal	`reset_n : in std_logic; -- CPU reset signal, active low`
12
13			`-- External interrupt input:`
14			`external_interrupt : in std_logic;`
15
16			`-- GPIO pins, must be inout to use with the GPIO module:`
17			`switches : inout std_logic_vector(15 downto 0);`
18			`leds : inout std_logic_vector(15 downto 0);`
19
20	61	skordal	`-- UART pins:`
21	7	skordal	`uart_txd : out std_logic;`
22	61	skordal	`uart_rxd : in std_logic;`
23
24			`-- 7-Segment display pins:`
25			`seg7_anode : out std_logic_vector(7 downto 0);`
26			`seg7_cathode : out std_logic_vector(6 downto 0)`
27	7	skordal	`);`
28			`end entity toplevel;`
29
30			`architecture behaviour of toplevel is`
31			`signal system_clk : std_logic;`
32			`signal timer_clk : std_logic;`
33
34			`-- Active high reset signal:`
35			`signal reset : std_logic;`
36
37			`-- IRQs:`
38			`signal irq : std_logic_vector(7 downto 0);`
39			`signal uart_irq_rts, uart_irq_recv : std_logic;`
40			`signal timer_irq : std_logic;`
41
42			`-- Processor wishbone interface:`
43			`signal p_adr_out : std_logic_vector(31 downto 0);`
44			`signal p_dat_out : std_logic_vector(31 downto 0);`
45			`signal p_dat_in : std_logic_vector(31 downto 0);`
46			`signal p_sel_out : std_logic_vector( 3 downto 0);`
47			`signal p_we_out : std_logic;`
48			`signal p_cyc_out, p_stb_out : std_logic;`
49			`signal p_ack_in : std_logic;`
50
51			`-- Instruction memory wishbone interface:`
52			`signal imem_adr_in : std_logic_vector(12 downto 0);`
53			`signal imem_dat_out : std_logic_vector(31 downto 0);`
54			`signal imem_cyc_in, imem_stb_in : std_logic;`
55			`signal imem_ack_out : std_logic;`
56
57			`-- Data memory wishbone interface:`
58			`signal dmem_adr_in : std_logic_vector(12 downto 0);`
59			`signal dmem_dat_in : std_logic_vector(31 downto 0);`
60			`signal dmem_dat_out : std_logic_vector(31 downto 0);`
61			`signal dmem_sel_in : std_logic_vector( 3 downto 0);`
62			`signal dmem_we_in : std_logic;`
63			`signal dmem_cyc_in, dmem_stb_in : std_logic;`
64			`signal dmem_ack_out : std_logic;`
65
66			`-- GPIO module I (switches) wishbone interface:`
67	61	skordal	`signal gpio1_adr_in : std_logic_vector( 1 downto 0);`
68	7	skordal	`signal gpio1_dat_in : std_logic_vector(31 downto 0);`
69			`signal gpio1_dat_out : std_logic_vector(31 downto 0);`
70			`signal gpio1_we_in : std_logic;`
71			`signal gpio1_cyc_in, gpio1_stb_in : std_logic;`
72			`signal gpio1_ack_out : std_logic;`
73
74			`-- GPIO module II (LEDs) wishbone interface:`
75	61	skordal	`signal gpio2_adr_in : std_logic_vector( 1 downto 0);`
76	7	skordal	`signal gpio2_dat_in : std_logic_vector(31 downto 0);`
77			`signal gpio2_dat_out : std_logic_vector(31 downto 0);`
78			`signal gpio2_we_in : std_logic;`
79			`signal gpio2_cyc_in, gpio2_stb_in : std_logic;`
80			`signal gpio2_ack_out : std_logic;`
81
82			`-- UART module wishbone interface:`
83			`signal uart_adr_in : std_logic_vector(1 downto 0);`
84			`signal uart_dat_in : std_logic_vector(7 downto 0);`
85			`signal uart_dat_out : std_logic_vector(7 downto 0);`
86			`signal uart_we_in : std_logic;`
87			`signal uart_cyc_in, uart_stb_in : std_logic;`
88			`signal uart_ack_out : std_logic;`
89
90			`-- Timer module wishbone interface:`
91	61	skordal	`signal timer_adr_in : std_logic_vector( 1 downto 0);`
92	7	skordal	`signal timer_dat_in : std_logic_vector(31 downto 0);`
93			`signal timer_dat_out : std_logic_vector(31 downto 0);`
94			`signal timer_we_in : std_logic;`
95			`signal timer_cyc_in, timer_stb_in : std_logic;`
96			`signal timer_ack_out : std_logic;`
97
98	61	skordal	`-- 7-Segment module wishbone interface:`
99			`signal seg7_adr_in : std_logic_vector( 0 downto 0);`
100			`signal seg7_dat_in : std_logic_vector(31 downto 0);`
101			`signal seg7_dat_out : std_logic_vector(31 downto 0);`
102			`signal seg7_we_in : std_logic;`
103			`signal seg7_cyc_in, seg7_stb_in : std_logic;`
104			`signal seg7_ack_out : std_logic;`
105
106	7	skordal	`-- Dummy module interface:`
107			`signal dummy_dat_in : std_logic_vector(31 downto 0);`
108			`signal dummy_dat_out : std_logic_vector(31 downto 0);`
109			`signal dummy_we_in : std_logic;`
110			`signal dummy_cyc_in, dummy_stb_in : std_logic;`
111			`signal dummy_ack_out : std_logic;`
112
113			`-- Address decoder signals:`
114			`type ad_state_type is (IDLE, BUSY);`
115			`signal ad_state : ad_state_type;`
116
117			`type module_name is (`
118			`MODULE_IMEM, MODULE_DMEM, -- Memory modules`
119			`MODULE_GPIO1, MODULE_GPIO2, -- GPIO modules`
120			`MODULE_UART, -- UART module`
121			`MODULE_TIMER, -- Timer module`
122	61	skordal	`MODULE_7SEG, -- 7-Segment module`
123	7	skordal	`MODULE_DUMMY, -- Dummy module, used for invalid addresses`
124	21	skordal	`MODULE_NONE -- Boring no-module mode`
125	7	skordal	`);`
126			`signal active_module : module_name;`
127
128			`begin`
129
130			`reset <= not reset_n;`
131			`irq <= (`
132
133			`1 => uart_irq_rts, 2 => uart_irq_recv,`
134			`5 => timer_irq, others => '0'`
135			`);`
136
137			`clkgen: entity work.clock_generator`
138			`port map(`
139			`clk => clk,`
140			`system_clk => system_clk,`
141			`timer_clk => timer_clk`
142			`);`
143
144			`processor: entity work.pp_potato`
145			`port map(`
146			`clk => system_clk,`
147	58	skordal	`timer_clk => timer_clk,`
148	7	skordal	`reset => reset,`
149			`irq => irq,`
150			`fromhost_data => (others => '0'),`
151			`fromhost_updated => '0',`
152			`tohost_data => open,`
153			`tohost_updated => open,`
154			`wb_adr_out => p_adr_out,`
155			`wb_dat_out => p_dat_out,`
156			`wb_dat_in => p_dat_in,`
157			`wb_sel_out => p_sel_out,`
158			`wb_we_out => p_we_out,`
159			`wb_cyc_out => p_cyc_out,`
160			`wb_stb_out => p_stb_out,`
161			`wb_ack_in => p_ack_in`
162			`);`
163
164			`imem: entity work.imem_wrapper`
165			`port map(`
166			`clk => system_clk,`
167			`reset => reset,`
168			`wb_adr_in => imem_adr_in,`
169			`wb_dat_out => imem_dat_out,`
170			`wb_cyc_in => imem_cyc_in,`
171			`wb_stb_in => imem_stb_in,`
172			`wb_ack_out => imem_ack_out`
173			`);`
174
175			`dmem: entity work.pp_soc_memory`
176			`generic map(`
177			`MEMORY_SIZE => 8192`
178			`) port map(`
179			`clk => system_clk,`
180			`reset => reset,`
181			`wb_adr_in => dmem_adr_in,`
182			`wb_dat_in => dmem_dat_in,`
183			`wb_dat_out => dmem_dat_out,`
184			`wb_sel_in => dmem_sel_in,`
185			`wb_we_in => dmem_we_in,`
186			`wb_cyc_in => dmem_cyc_in,`
187			`wb_stb_in => dmem_stb_in,`
188			`wb_ack_out => dmem_ack_out`
189			`);`
190
191			`gpio1: entity work.pp_soc_gpio`
192			`generic map(`
193			`NUM_GPIOS => 16`
194			`) port map(`
195			`clk => system_clk,`
196			`reset => reset,`
197			`gpio => switches,`
198			`wb_adr_in => gpio1_adr_in,`
199			`wb_dat_in => gpio1_dat_in,`
200			`wb_dat_out => gpio1_dat_out,`
201			`wb_cyc_in => gpio1_cyc_in,`
202			`wb_stb_in => gpio1_stb_in,`
203			`wb_we_in => gpio1_we_in,`
204			`wb_ack_out => gpio1_ack_out`
205			`);`
206
207			`gpio2: entity work.pp_soc_gpio`
208			`generic map(`
209			`NUM_GPIOS => 16`
210			`) port map(`
211			`clk => system_clk,`
212			`reset => reset,`
213			`gpio => leds,`
214			`wb_adr_in => gpio2_adr_in,`
215			`wb_dat_in => gpio2_dat_in,`
216			`wb_dat_out => gpio2_dat_out,`
217			`wb_cyc_in => gpio2_cyc_in,`
218			`wb_stb_in => gpio2_stb_in,`
219			`wb_we_in => gpio2_we_in,`
220			`wb_ack_out => gpio2_ack_out`
221			`);`
222
223			`uart1: entity work.pp_soc_uart`
224			`generic map(`
225			`FIFO_DEPTH => 64,`
226	45	skordal	`SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz`
227			`--SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz`
228	7	skordal	`) port map(`
229			`clk => system_clk,`
230			`reset => reset,`
231			`txd => uart_txd,`
232			`rxd => uart_rxd,`
233			`irq_send_buffer_empty => uart_irq_rts,`
234			`irq_data_received => uart_irq_recv,`
235			`wb_adr_in => uart_adr_in,`
236			`wb_dat_in => uart_dat_in,`
237			`wb_dat_out => uart_dat_out,`
238			`wb_cyc_in => uart_cyc_in,`
239			`wb_stb_in => uart_stb_in,`
240			`wb_we_in => uart_we_in,`
241			`wb_ack_out => uart_ack_out`
242			`);`
243
244			`timer1: entity work.pp_soc_timer`
245			`port map(`
246			`clk => system_clk,`
247			`reset => reset,`
248			`irq => timer_irq,`
249			`wb_adr_in => timer_adr_in,`
250			`wb_dat_in => timer_dat_in,`
251			`wb_dat_out => timer_dat_out,`
252			`wb_cyc_in => timer_cyc_in,`
253			`wb_stb_in => timer_stb_in,`
254			`wb_we_in => timer_we_in,`
255			`wb_ack_out => timer_ack_out`
256			`);`
257
258	61	skordal	`seg7_1: entity work.pp_soc_7seg`
259			`generic map(`
260			`SWITCH_COUNT => 50000 -- For 50 MHz`
261			`) port map(`
262			`clk => system_clk,`
263			`reset => reset,`
264			`seg7_anode => seg7_anode,`
265			`seg7_cathode => seg7_cathode,`
266			`wb_adr_in => seg7_adr_in,`
267			`wb_dat_in => seg7_dat_in,`
268			`wb_dat_out => seg7_dat_out,`
269			`wb_cyc_in => seg7_cyc_in,`
270			`wb_stb_in => seg7_stb_in,`
271			`wb_we_in => seg7_we_in,`
272			`wb_ack_out => seg7_ack_out`
273			`);`
274
275	7	skordal	`dummy: entity work.pp_soc_dummy`
276			`port map(`
277			`clk => system_clk,`
278			`reset => reset,`
279			`wb_dat_in => dummy_dat_in,`
280			`wb_dat_out => dummy_dat_out,`
281			`wb_cyc_in => dummy_cyc_in,`
282			`wb_stb_in => dummy_stb_in,`
283			`wb_we_in => dummy_we_in,`
284			`wb_ack_out => dummy_ack_out`
285			`);`
286
287			`imem_cyc_in <= p_cyc_out when active_module = MODULE_IMEM else '0';`
288			`dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';`
289			`gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';`
290			`gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';`
291			`uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';`
292			`timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';`
293	61	skordal	`seg7_cyc_in <= p_cyc_out when active_module = MODULE_7SEG else '0';`
294	7	skordal	`dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';`
295
296			`imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';`
297			`dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';`
298			`gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';`
299			`gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';`
300			`uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';`
301			`timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';`
302	61	skordal	`seg7_stb_in <= p_stb_out when active_module = MODULE_7SEG else '0';`
303	7	skordal	`dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';`
304
305			`imem_adr_in <= p_adr_out(12 downto 0);`
306			`dmem_adr_in <= p_adr_out(12 downto 0);`
307			`gpio1_adr_in <= p_adr_out(3 downto 2);`
308			`gpio2_adr_in <= p_adr_out(3 downto 2);`
309			`uart_adr_in <= p_adr_out(3 downto 2);`
310			`timer_adr_in <= p_adr_out(3 downto 2);`
311	61	skordal	`seg7_adr_in <= p_adr_out(2 downto 2);`
312	7	skordal
313			`dmem_dat_in <= p_dat_out;`
314			`gpio1_dat_in <= p_dat_out;`
315			`gpio2_dat_in <= p_dat_out;`
316			`uart_dat_in <= p_dat_out(7 downto 0);`
317			`timer_dat_in <= p_dat_out;`
318	61	skordal	`seg7_dat_in <= p_dat_out;`
319	7	skordal	`dummy_dat_in <= p_dat_out;`
320
321			`dmem_sel_in <= p_sel_out;`
322
323			`gpio1_we_in <= p_we_out;`
324			`gpio2_we_in <= p_we_out;`
325			`dmem_we_in <= p_we_out;`
326			`uart_we_in <= p_we_out;`
327			`timer_we_in <= p_we_out;`
328	61	skordal	`seg7_we_in <= p_we_out;`
329	7	skordal	`dummy_we_in <= p_we_out;`
330
331			`address_decoder: process(system_clk)`
332			`begin`
333			`if rising_edge(system_clk) then`
334			`if reset = '1' then`
335			`ad_state <= IDLE;`
336			`active_module <= MODULE_NONE;`
337			`else`
338			`case ad_state is`
339			`when IDLE =>`
340	45	skordal	`if p_cyc_out = '1' then`
341	7	skordal	`if p_adr_out(31 downto 13) = b"0000000000000000000" then`
342			`active_module <= MODULE_IMEM;`
343			`ad_state <= BUSY;`
344			`elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000`
345			`active_module <= MODULE_DMEM;`
346			`ad_state <= BUSY;`
347			`elsif p_adr_out(31 downto 11) = b"000000000000000001000" then -- 0x4000`
348			`active_module <= MODULE_GPIO1;`
349			`ad_state <= BUSY;`
350			`elsif p_adr_out(31 downto 11) = b"000000000000000001001" then -- 0x4800`
351			`active_module <= MODULE_GPIO2;`
352			`ad_state <= BUSY;`
353			`elsif p_adr_out(31 downto 11) = b"000000000000000001010" then -- 0x5000`
354			`active_module <= MODULE_UART;`
355			`ad_state <= BUSY;`
356			`elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800`
357			`active_module <= MODULE_TIMER;`
358			`ad_state <= BUSY;`
359	61	skordal	`elsif p_adr_out(31 downto 11) = b"000000000000000001100" then -- 0x6000`
360			`active_module <= MODULE_7SEG;`
361			`ad_state <= BUSY;`
362	7	skordal	`else`
363			`active_module <= MODULE_DUMMY;`
364			`ad_state <= BUSY;`
365			`end if;`
366	45	skordal	`else`
367			`active_module <= MODULE_NONE;`
368	7	skordal	`end if;`
369			`when BUSY =>`
370			`if p_cyc_out = '0' then`
371			`active_module <= MODULE_NONE;`
372			`ad_state <= IDLE;`
373			`end if;`
374			`end case;`
375			`end if;`
376			`end if;`
377			`end process address_decoder;`
378
379			`module_mux: process(active_module, imem_ack_out, imem_dat_out, dmem_ack_out, dmem_dat_out,`
380			`gpio1_ack_out, gpio1_dat_out, gpio2_ack_out, gpio2_dat_out, uart_ack_out, uart_dat_out,`
381			`timer_ack_out, timer_dat_out, dummy_ack_out, dummy_dat_out)`
382			`begin`
383			`case active_module is`
384			`when MODULE_IMEM =>`
385			`p_ack_in <= imem_ack_out;`
386			`p_dat_in <= imem_dat_out;`
387			`when MODULE_DMEM =>`
388			`p_ack_in <= dmem_ack_out;`
389			`p_dat_in <= dmem_dat_out;`
390			`when MODULE_GPIO1 =>`
391			`p_ack_in <= gpio1_ack_out;`
392			`p_dat_in <= gpio1_dat_out;`
393			`when MODULE_GPIO2 =>`
394			`p_ack_in <= gpio2_ack_out;`
395			`p_dat_in <= gpio2_dat_out;`
396			`when MODULE_UART =>`
397			`p_ack_in <= uart_ack_out;`
398			`p_dat_in <= (31 downto 8 => '0') & uart_dat_out;`
399			`when MODULE_TIMER =>`
400			`p_ack_in <= timer_ack_out;`
401			`p_dat_in <= timer_dat_out;`
402	61	skordal	`when MODULE_7SEG =>`
403			`p_ack_in <= seg7_ack_out;`
404			`p_dat_in <= seg7_dat_out;`
405	7	skordal	`when MODULE_DUMMY =>`
406			`p_ack_in <= dummy_ack_out;`
407			`p_dat_in <= dummy_dat_out;`
408			`when MODULE_NONE =>`
409			`p_ack_in <= '0';`
410			`p_dat_in <= (others => '0');`
411			`end case;`
412			`end process module_mux;`
413
414			`end architecture behaviour;`

Browse

Tools

Subversion Repositories potato

[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Blame information for rev 61