OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [riscv-tests/] [addi.S] - Blame information for rev 6

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 skordal
# See LICENSE for license details.
2
 
3
#*****************************************************************************
4
# addi.S
5
#-----------------------------------------------------------------------------
6
#
7
# Test addi instruction.
8
#
9
 
10
#include "riscv_test.h"
11
#include "test_macros.h"
12
 
13
RVTEST_RV32U
14
RVTEST_CODE_BEGIN
15
 
16
  #-------------------------------------------------------------
17
  # Arithmetic tests
18
  #-------------------------------------------------------------
19
 
20
  TEST_IMM_OP( 2,  addi, 0x00000000, 0x00000000, 0x000 );
21
  TEST_IMM_OP( 3,  addi, 0x00000002, 0x00000001, 0x001 );
22
  TEST_IMM_OP( 4,  addi, 0x0000000a, 0x00000003, 0x007 );
23
 
24
  TEST_IMM_OP( 5,  addi, 0xfffff800, 0x00000000, 0x800 );
25
  TEST_IMM_OP( 6,  addi, 0x80000000, 0x80000000, 0x000 );
26
  TEST_IMM_OP( 7,  addi, 0x7ffff800, 0x80000000, 0x800 );
27
 
28
  TEST_IMM_OP( 8,  addi, 0x000007ff, 0x00000000, 0x7ff );
29
  TEST_IMM_OP( 9,  addi, 0x7fffffff, 0x7fffffff, 0x000 );
30
  TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff );
31
 
32
  TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff );
33
  TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 );
34
 
35
  TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff );
36
  TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 );
37
  TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff );
38
 
39
  TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 );
40
 
41
  #-------------------------------------------------------------
42
  # Source/Destination tests
43
  #-------------------------------------------------------------
44
 
45
  TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
46
 
47
  #-------------------------------------------------------------
48
  # Bypassing tests
49
  #-------------------------------------------------------------
50
 
51
  TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
52
  TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
53
  TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13,  9 );
54
 
55
  TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
56
  TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
57
  TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13,  9 );
58
 
59
  TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
60
  TEST_IMM_ZERODEST( 25, addi, 33, 50 );
61
 
62
  TEST_PASSFAIL
63
 
64
RVTEST_CODE_END
65
 
66
  .data
67
RVTEST_DATA_BEGIN
68
 
69
  TEST_DATA
70
 
71
RVTEST_DATA_END

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.