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[/] [potato/] [trunk/] [riscv-tests/] [ma_addr.S] - Blame information for rev 58

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# See LICENSE for license details.
 
#*****************************************************************************
# ma_addr.S
#-----------------------------------------------------------------------------
#
# Test misaligned ld/st trap.
#
 
#include "riscv_test.h"
#include "test_macros.h"
 
#include "riscv_test.h"
#undef RVTEST_RV64S
#define RVTEST_RV64S RVTEST_RV32M
#define __MACHINE_MODE
 
RVTEST_RV32M
RVTEST_CODE_BEGIN
 
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sepc mepc
#define stvec_handler mtvec_handler
 
  la s0, stvec_handler
 
  # indicate it's a load test
  li s1, 0
 
#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
  li TESTNUM, testnum; \
  insn x0, offset(base); \
  j fail \
 
  MISALIGNED_LDST_TEST(2,  lh,  s0, 1)
  MISALIGNED_LDST_TEST(3,  lhu, s0, 1)
  MISALIGNED_LDST_TEST(4,  lw,  s0, 1)
  MISALIGNED_LDST_TEST(5,  lw,  s0, 2)
  MISALIGNED_LDST_TEST(6,  lw,  s0, 3)
 
#ifdef __riscv64
  MISALIGNED_LDST_TEST(7,  lwu, s0, 1)
  MISALIGNED_LDST_TEST(8,  lwu, s0, 2)
  MISALIGNED_LDST_TEST(9,  lwu, s0, 3)
 
  MISALIGNED_LDST_TEST(10, ld, s0, 1)
  MISALIGNED_LDST_TEST(11, ld, s0, 2)
  MISALIGNED_LDST_TEST(12, ld, s0, 3)
  MISALIGNED_LDST_TEST(13, ld, s0, 4)
  MISALIGNED_LDST_TEST(14, ld, s0, 5)
  MISALIGNED_LDST_TEST(15, ld, s0, 6)
  MISALIGNED_LDST_TEST(16, ld, s0, 7)
#endif
 
  # indicate it's a store test
  li s1, 1
 
  MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
  MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
  MISALIGNED_LDST_TEST(24,  sw,  s0, 2)
  MISALIGNED_LDST_TEST(25,  sw,  s0, 3)
 
#ifdef __riscv64
  MISALIGNED_LDST_TEST(26, sd, s0, 1)
  MISALIGNED_LDST_TEST(27, sd, s0, 2)
  MISALIGNED_LDST_TEST(28, sd, s0, 3)
  MISALIGNED_LDST_TEST(29, sd, s0, 4)
  MISALIGNED_LDST_TEST(30, sd, s0, 5)
  MISALIGNED_LDST_TEST(31, sd, s0, 6)
  MISALIGNED_LDST_TEST(32, sd, s0, 7)
#endif
 
  TEST_PASSFAIL
 
  .align 3
stvec_handler:
  bnez s1, test_store
 
test_load:
  li t1, CAUSE_MISALIGNED_LOAD
  csrr t0, scause
  bne t0, t1, fail
  csrr t0, sepc
  addi t0, t0, 8
  csrw sepc, t0
  sret
 
test_store:
  li t1, CAUSE_MISALIGNED_STORE
  csrr t0, scause
  bne t0, t1, fail
  csrr t0, sepc
  addi t0, t0, 8
  csrw sepc, t0
  sret
 
RVTEST_CODE_END
 
  .data
RVTEST_DATA_BEGIN
 
  TEST_DATA
 
RVTEST_DATA_END

Line No.	Rev	Author	Line
1	50	skordal	`# See LICENSE for license details.`
2
3			`#*****************************************************************************`
4			`# ma_addr.S`
5			`#-----------------------------------------------------------------------------`
6			`#`
7			`# Test misaligned ld/st trap.`
8			`#`
9
10			`#include "riscv_test.h"`
11			`#include "test_macros.h"`
12
13			`#include "riscv_test.h"`
14			`#undef RVTEST_RV64S`
15			`#define RVTEST_RV64S RVTEST_RV32M`
16			`#define __MACHINE_MODE`
17
18			`RVTEST_RV32M`
19			`RVTEST_CODE_BEGIN`
20
21			`#define sscratch mscratch`
22			`#define sstatus mstatus`
23			`#define scause mcause`
24			`#define sepc mepc`
25			`#define stvec_handler mtvec_handler`
26
27			`la s0, stvec_handler`
28
29			`# indicate it's a load test`
30			`li s1, 0`
31
32			`#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \`
33			`li TESTNUM, testnum; \`
34			`insn x0, offset(base); \`
35			`j fail \`
36
37			`MISALIGNED_LDST_TEST(2, lh, s0, 1)`
38			`MISALIGNED_LDST_TEST(3, lhu, s0, 1)`
39			`MISALIGNED_LDST_TEST(4, lw, s0, 1)`
40			`MISALIGNED_LDST_TEST(5, lw, s0, 2)`
41			`MISALIGNED_LDST_TEST(6, lw, s0, 3)`
42
43			`#ifdef __riscv64`
44			`MISALIGNED_LDST_TEST(7, lwu, s0, 1)`
45			`MISALIGNED_LDST_TEST(8, lwu, s0, 2)`
46			`MISALIGNED_LDST_TEST(9, lwu, s0, 3)`
47
48			`MISALIGNED_LDST_TEST(10, ld, s0, 1)`
49			`MISALIGNED_LDST_TEST(11, ld, s0, 2)`
50			`MISALIGNED_LDST_TEST(12, ld, s0, 3)`
51			`MISALIGNED_LDST_TEST(13, ld, s0, 4)`
52			`MISALIGNED_LDST_TEST(14, ld, s0, 5)`
53			`MISALIGNED_LDST_TEST(15, ld, s0, 6)`
54			`MISALIGNED_LDST_TEST(16, ld, s0, 7)`
55			`#endif`
56
57			`# indicate it's a store test`
58			`li s1, 1`
59
60			`MISALIGNED_LDST_TEST(22, sh, s0, 1)`
61			`MISALIGNED_LDST_TEST(23, sw, s0, 1)`
62			`MISALIGNED_LDST_TEST(24, sw, s0, 2)`
63			`MISALIGNED_LDST_TEST(25, sw, s0, 3)`
64
65			`#ifdef __riscv64`
66			`MISALIGNED_LDST_TEST(26, sd, s0, 1)`
67			`MISALIGNED_LDST_TEST(27, sd, s0, 2)`
68			`MISALIGNED_LDST_TEST(28, sd, s0, 3)`
69			`MISALIGNED_LDST_TEST(29, sd, s0, 4)`
70			`MISALIGNED_LDST_TEST(30, sd, s0, 5)`
71			`MISALIGNED_LDST_TEST(31, sd, s0, 6)`
72			`MISALIGNED_LDST_TEST(32, sd, s0, 7)`
73			`#endif`
74
75			`TEST_PASSFAIL`
76
77			`.align 3`
78			`stvec_handler:`
79			`bnez s1, test_store`
80
81			`test_load:`
82			`li t1, CAUSE_MISALIGNED_LOAD`
83			`csrr t0, scause`
84			`bne t0, t1, fail`
85			`csrr t0, sepc`
86			`addi t0, t0, 8`
87			`csrw sepc, t0`
88			`sret`
89
90			`test_store:`
91			`li t1, CAUSE_MISALIGNED_STORE`
92			`csrr t0, scause`
93			`bne t0, t1, fail`
94			`csrr t0, sepc`
95			`addi t0, t0, 8`
96			`csrw sepc, t0`
97			`sret`
98
99			`RVTEST_CODE_END`
100
101			`.data`
102			`RVTEST_DATA_BEGIN`
103
104			`TEST_DATA`
105
106			`RVTEST_DATA_END`

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[/] [potato/] [trunk/] [riscv-tests/] [ma_addr.S] - Blame information for rev 58