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[/] [potato/] [trunk/] [riscv-tests/] [riscv_test.h] - Blame information for rev 18

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// See LICENSE for license details.
 
#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
#define _ENV_PHYSICAL_SINGLE_CORE_H
 
#include "encoding.h"
//#include "../hwacha_xcpt.h"
 
//-----------------------------------------------------------------------
// Begin Macro
//-----------------------------------------------------------------------
 
#define RVTEST_RV64U                                                    \
  .macro init;                                                          \
  .endm
 
#define RVTEST_RV64UF                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV64UV                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  RVTEST_VEC_ENABLE;                                                    \
  .endm
 
#define RVTEST_RV32U                                                    \
  .macro init;                                                          \
  RVTEST_32_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV32UF                                                   \
  .macro init;                                                          \
  RVTEST_32_ENABLE;                                                     \
  RVTEST_FP_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV32UV                                                   \
  .macro init;                                                          \
  RVTEST_32_ENABLE;                                                     \
  RVTEST_FP_ENABLE;                                                     \
  RVTEST_VEC_ENABLE;                                                    \
  .endm
 
#define RVTEST_RV64S                                                    \
  .macro init;                                                          \
  .endm
 
#define RVTEST_RV32S                                                    \
  .macro init;                                                          \
  RVTEST_32_ENABLE;                                                     \
  .endm
 
#define RVTEST_32_ENABLE                                                \
  li a0, SR_S64;                                                        \
  csrc status, a0;                                                      \
 
#define RVTEST_FP_ENABLE                                                \
  li a0, SR_EF;                                                         \
  csrs status, a0;                                                      \
  csrr a1, status;                                                      \
  and a0, a0, a1;                                                       \
  bnez a0, 2f;                                                          \
  RVTEST_PASS;                                                          \
2:fssr x0;                                                              \
 
#define RVTEST_VEC_ENABLE                                               \
  li a0, SR_EA;                                                         \
  csrs status, a0;                                                      \
  csrr a1, status;                                                      \
  and a0, a0, a1;                                                       \
  bnez a0, 2f;                                                          \
  RVTEST_PASS;                                                          \
2:                                                                      \
 
#define RISCV_MULTICORE_DISABLE                                         \
  csrr a0, hartid;                                                      \
  1: bnez a0, 1b;                                                       \
 
#define EXTRA_INIT
#define EXTRA_INIT_TIMER
 
#define RVTEST_CODE_BEGIN                                               \
        .text;                                                          \
        .align  4;                                                      \
        .global _start;                                                 \
_start:                                                                 \
        RISCV_MULTICORE_DISABLE;                                        \
        init;                                                           \
        EXTRA_INIT;                                                     \
        EXTRA_INIT_TIMER;                                               \
 
//-----------------------------------------------------------------------
// End Macro
//-----------------------------------------------------------------------
 
#define RVTEST_CODE_END                                                 \
 
//-----------------------------------------------------------------------
// Pass/Fail Macro
//-----------------------------------------------------------------------
 
#define RVTEST_PASS                                                     \
        fence;                                                          \
        csrw tohost, 1;                                                 \
1:      j 1b;                                                           \
 
#define TESTNUM x28
#define RVTEST_FAIL                                                     \
        fence;                                                          \
        beqz TESTNUM, 1f;                                               \
        sll TESTNUM, TESTNUM, 1;                                        \
        or TESTNUM, TESTNUM, 1;                                         \
        csrw tohost, TESTNUM;                                           \
1:      j 1b;                                                           \
 
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
 
#define EXTRA_DATA
 
#define RVTEST_DATA_BEGIN EXTRA_DATA .align 4; .global begin_signature; begin_signature:
#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
 
#endif

Line No.	Rev	Author	Line
1	6	skordal	`// See LICENSE for license details.`
2
3			`#ifndef _ENV_PHYSICAL_SINGLE_CORE_H`
4			`#define _ENV_PHYSICAL_SINGLE_CORE_H`
5
6			`#include "encoding.h"`
7			`//#include "../hwacha_xcpt.h"`
8
9			`//-----------------------------------------------------------------------`
10			`// Begin Macro`
11			`//-----------------------------------------------------------------------`
12
13			`#define RVTEST_RV64U \`
14			`.macro init; \`
15			`.endm`
16
17			`#define RVTEST_RV64UF \`
18			`.macro init; \`
19			`RVTEST_FP_ENABLE; \`
20			`.endm`
21
22			`#define RVTEST_RV64UV \`
23			`.macro init; \`
24			`RVTEST_FP_ENABLE; \`
25			`RVTEST_VEC_ENABLE; \`
26			`.endm`
27
28			`#define RVTEST_RV32U \`
29			`.macro init; \`
30			`RVTEST_32_ENABLE; \`
31			`.endm`
32
33			`#define RVTEST_RV32UF \`
34			`.macro init; \`
35			`RVTEST_32_ENABLE; \`
36			`RVTEST_FP_ENABLE; \`
37			`.endm`
38
39			`#define RVTEST_RV32UV \`
40			`.macro init; \`
41			`RVTEST_32_ENABLE; \`
42			`RVTEST_FP_ENABLE; \`
43			`RVTEST_VEC_ENABLE; \`
44			`.endm`
45
46			`#define RVTEST_RV64S \`
47			`.macro init; \`
48			`.endm`
49
50			`#define RVTEST_RV32S \`
51			`.macro init; \`
52			`RVTEST_32_ENABLE; \`
53			`.endm`
54
55			`#define RVTEST_32_ENABLE \`
56			`li a0, SR_S64; \`
57			`csrc status, a0; \`
58
59			`#define RVTEST_FP_ENABLE \`
60			`li a0, SR_EF; \`
61			`csrs status, a0; \`
62			`csrr a1, status; \`
63			`and a0, a0, a1; \`
64			`bnez a0, 2f; \`
65			`RVTEST_PASS; \`
66			`2:fssr x0; \`
67
68			`#define RVTEST_VEC_ENABLE \`
69			`li a0, SR_EA; \`
70			`csrs status, a0; \`
71			`csrr a1, status; \`
72			`and a0, a0, a1; \`
73			`bnez a0, 2f; \`
74			`RVTEST_PASS; \`
75			`2: \`
76
77			`#define RISCV_MULTICORE_DISABLE \`
78			`csrr a0, hartid; \`
79			`1: bnez a0, 1b; \`
80
81			`#define EXTRA_INIT`
82			`#define EXTRA_INIT_TIMER`
83
84			`#define RVTEST_CODE_BEGIN \`
85			`.text; \`
86			`.align 4; \`
87			`.global _start; \`
88			`_start: \`
89			`RISCV_MULTICORE_DISABLE; \`
90			`init; \`
91			`EXTRA_INIT; \`
92			`EXTRA_INIT_TIMER; \`
93
94			`//-----------------------------------------------------------------------`
95			`// End Macro`
96			`//-----------------------------------------------------------------------`
97
98			`#define RVTEST_CODE_END \`
99
100			`//-----------------------------------------------------------------------`
101			`// Pass/Fail Macro`
102			`//-----------------------------------------------------------------------`
103
104			`#define RVTEST_PASS \`
105			`fence; \`
106			`csrw tohost, 1; \`
107			`1: j 1b; \`
108
109			`#define TESTNUM x28`
110			`#define RVTEST_FAIL \`
111			`fence; \`
112			`beqz TESTNUM, 1f; \`
113			`sll TESTNUM, TESTNUM, 1; \`
114			`or TESTNUM, TESTNUM, 1; \`
115			`csrw tohost, TESTNUM; \`
116			`1: j 1b; \`
117
118			`//-----------------------------------------------------------------------`
119			`// Data Section Macro`
120			`//-----------------------------------------------------------------------`
121
122			`#define EXTRA_DATA`
123
124			`#define RVTEST_DATA_BEGIN EXTRA_DATA .align 4; .global begin_signature; begin_signature:`
125			`#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:`
126
127			`#endif`

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[/] [potato/] [trunk/] [riscv-tests/] [riscv_test.h] - Blame information for rev 18