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[/] [potato/] [trunk/] [riscv-tests/] [riscv_test.h] - Blame information for rev 62

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// See LICENSE for license details.
 
#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
#define _ENV_PHYSICAL_SINGLE_CORE_H
 
#include "encoding.h"
#include "hwacha_xcpt.h"
 
//-----------------------------------------------------------------------
// Begin Macro
//-----------------------------------------------------------------------
 
#define RVTEST_RV64U                                                    \
  .macro init;                                                          \
  .endm
 
#define RVTEST_RV64UF                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV64UV                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  RVTEST_VEC_ENABLE;                                                    \
  .endm
 
#define RVTEST_RV32U                                                    \
  .macro init;                                                          \
  .endm
 
#define RVTEST_RV32UF                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  .endm
 
#define RVTEST_RV32UV                                                   \
  .macro init;                                                          \
  RVTEST_FP_ENABLE;                                                     \
  RVTEST_VEC_ENABLE;                                                    \
  .endm
 
#define RVTEST_RV64M                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_MACHINE;                                                \
  .endm
 
#define RVTEST_RV64S                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_SUPERVISOR;                                             \
  .endm
 
#define RVTEST_RV64SV                                                   \
  .macro init;                                                          \
  RVTEST_ENABLE_SUPERVISOR;                                             \
  RVTEST_VEC_ENABLE;                                                    \
  .endm
 
#define RVTEST_RV32M                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_MACHINE;                                                \
  .endm
 
#define RVTEST_RV32S                                                    \
  .macro init;                                                          \
  RVTEST_ENABLE_SUPERVISOR;                                             \
  .endm
 
#ifdef __riscv64
# define CHECK_XLEN csrr a0, mcpuid; bltz a0, 1f; RVTEST_PASS; 1:
#else
# define CHECK_XLEN csrr a0, mcpuid; bgez a0, 1f; RVTEST_PASS; 1:
#endif
 
#define RVTEST_ENABLE_SUPERVISOR                                        \
  li a0, MSTATUS_PRV1 & (MSTATUS_PRV1 >> 1);                            \
  csrs mstatus, a0;                                                     \
 
#define RVTEST_ENABLE_MACHINE                                           \
  li a0, MSTATUS_PRV1;                                                  \
  csrs mstatus, a0;                                                     \
 
#define RVTEST_FP_ENABLE                                                \
  li a0, MSTATUS_FS & (MSTATUS_FS >> 1);                                \
  csrs mstatus, a0;                                                     \
  csrr a0, mcpuid;                                                      \
  andi a0, a0, 1 << ('D' - 'A'); /* test for D extension */             \
  bnez a0, 1f;                                                          \
  RVTEST_PASS; /* "pass" the test if FPU not present */                 \
1:csrwi fcsr, 0
 
#define RVTEST_VEC_ENABLE                                               \
  li a0, SSTATUS_XS & (SSTATUS_XS >> 1);                                \
  csrs sstatus, a0;                                                     \
  csrr a1, sstatus;                                                     \
  and a0, a0, a1;                                                       \
  bnez a0, 2f;                                                          \
  RVTEST_PASS;                                                          \
2:                                                                      \
 
#define RISCV_MULTICORE_DISABLE                                         \
  csrr a0, mhartid;                                                     \
  1: bnez a0, 1b
 
#define EXTRA_TVEC_USER
#define EXTRA_TVEC_SUPERVISOR
#define EXTRA_TVEC_HYPERVISOR
#define EXTRA_TVEC_MACHINE
#define EXTRA_INIT
#define EXTRA_INIT_TIMER
 
#define RVTEST_CODE_BEGIN                                               \
        .text;                                                          \
        .align  6;                                                      \
        .weak stvec_handler;                                            \
        .weak mtvec_handler;                                            \
tvec_user:                                                              \
        EXTRA_TVEC_USER;                                                \
        /* test whether the test came from pass/fail */                 \
        la t5, ecall;                                                   \
        csrr t6, mepc;                                                  \
        beq t5, t6, write_tohost;                                       \
        /* test whether the stvec_handler target exists */              \
        la t5, stvec_handler;                                           \
        bnez t5, mrts_routine;                                          \
        /* test whether the mtvec_handler target exists */              \
        la t5, mtvec_handler;                                           \
        bnez t5, mtvec_handler;                                         \
        /* some other exception occurred */                             \
        j other_exception;                                              \
        .align  6;                                                      \
tvec_supervisor:                                                        \
        EXTRA_TVEC_SUPERVISOR;                                          \
        csrr t5, mcause;                                                \
        bgez t5, tvec_user;                                             \
  mrts_routine:                                                         \
        mrts;                                                           \
        .align  6;                                                      \
tvec_hypervisor:                                                        \
        EXTRA_TVEC_HYPERVISOR;                                          \
        /* renting some space out here */                               \
  other_exception:                                                      \
  1:    ori TESTNUM, TESTNUM, 1337; /* some other exception occurred */ \
  write_tohost:                                                         \
        csrw mtohost, TESTNUM;                                          \
        j write_tohost;                                                 \
        .align  6;                                                      \
tvec_machine:                                                           \
        EXTRA_TVEC_MACHINE;                                             \
        la t5, ecall;                                                   \
        csrr t6, mepc;                                                  \
        beq t5, t6, write_tohost;                                       \
        la t5, mtvec_handler;                                           \
        bnez t5, mtvec_handler;                                         \
        j other_exception;                                              \
        .align  6;                                                      \
        .globl _start;                                                  \
_start:                                                                 \
        RISCV_MULTICORE_DISABLE;                                        \
        CHECK_XLEN;                                                     \
        la t0, stvec_handler;                                           \
        csrw stvec, t0;                                                 \
        li t0, MSTATUS_PRV1 | MSTATUS_PRV2 | MSTATUS_IE1 | MSTATUS_IE2; \
        csrc mstatus, t0;                                               \
        init;                                                           \
        EXTRA_INIT;                                                     \
        EXTRA_INIT_TIMER;                                               \
        la t0, 1f;                                                      \
        csrw mepc, t0;                                                  \
        csrr a0, mhartid;                                               \
        eret;                                                           \
1:
 
//-----------------------------------------------------------------------
// End Macro
//-----------------------------------------------------------------------
 
#define RVTEST_CODE_END                                                 \
ecall:  ecall;                                                          \
        j ecall
 
//-----------------------------------------------------------------------
// Pass/Fail Macro
//-----------------------------------------------------------------------
 
#define RVTEST_PASS                                                     \
        fence;                                                          \
        li TESTNUM, 1;                                                  \
        j ecall
 
#define TESTNUM x28
#define RVTEST_FAIL                                                     \
        fence;                                                          \
1:      beqz TESTNUM, 1b;                                               \
        sll TESTNUM, TESTNUM, 1;                                        \
        or TESTNUM, TESTNUM, 1;                                         \
        j ecall
 
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
 
#define EXTRA_DATA
 
#define RVTEST_DATA_BEGIN EXTRA_DATA .align 4; .global begin_signature; begin_signature:
#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
 
#endif

Line No.	Rev	Author	Line
1	6	skordal	`// See LICENSE for license details.`
2
3			`#ifndef _ENV_PHYSICAL_SINGLE_CORE_H`
4			`#define _ENV_PHYSICAL_SINGLE_CORE_H`
5
6			`#include "encoding.h"`
7	58	skordal	`#include "hwacha_xcpt.h"`
8	6	skordal
9			`//-----------------------------------------------------------------------`
10			`// Begin Macro`
11			`//-----------------------------------------------------------------------`
12
13			`#define RVTEST_RV64U \`
14			`.macro init; \`
15			`.endm`
16
17			`#define RVTEST_RV64UF \`
18			`.macro init; \`
19			`RVTEST_FP_ENABLE; \`
20			`.endm`
21
22			`#define RVTEST_RV64UV \`
23			`.macro init; \`
24			`RVTEST_FP_ENABLE; \`
25			`RVTEST_VEC_ENABLE; \`
26			`.endm`
27
28			`#define RVTEST_RV32U \`
29			`.macro init; \`
30			`.endm`
31
32			`#define RVTEST_RV32UF \`
33			`.macro init; \`
34			`RVTEST_FP_ENABLE; \`
35			`.endm`
36
37			`#define RVTEST_RV32UV \`
38			`.macro init; \`
39			`RVTEST_FP_ENABLE; \`
40			`RVTEST_VEC_ENABLE; \`
41			`.endm`
42
43	58	skordal	`#define RVTEST_RV64M \`
44			`.macro init; \`
45			`RVTEST_ENABLE_MACHINE; \`
46			`.endm`
47
48	6	skordal	`#define RVTEST_RV64S \`
49			`.macro init; \`
50	58	skordal	`RVTEST_ENABLE_SUPERVISOR; \`
51	6	skordal	`.endm`
52
53	58	skordal	`#define RVTEST_RV64SV \`
54			`.macro init; \`
55			`RVTEST_ENABLE_SUPERVISOR; \`
56			`RVTEST_VEC_ENABLE; \`
57			`.endm`
58
59			`#define RVTEST_RV32M \`
60			`.macro init; \`
61			`RVTEST_ENABLE_MACHINE; \`
62			`.endm`
63
64	6	skordal	`#define RVTEST_RV32S \`
65			`.macro init; \`
66	58	skordal	`RVTEST_ENABLE_SUPERVISOR; \`
67	6	skordal	`.endm`
68
69	58	skordal	`#ifdef __riscv64`
70			`# define CHECK_XLEN csrr a0, mcpuid; bltz a0, 1f; RVTEST_PASS; 1:`
71			`#else`
72			`# define CHECK_XLEN csrr a0, mcpuid; bgez a0, 1f; RVTEST_PASS; 1:`
73			`#endif`
74	6	skordal
75	58	skordal	`#define RVTEST_ENABLE_SUPERVISOR \`
76			`li a0, MSTATUS_PRV1 & (MSTATUS_PRV1 >> 1); \`
77			`csrs mstatus, a0; \`
78
79			`#define RVTEST_ENABLE_MACHINE \`
80			`li a0, MSTATUS_PRV1; \`
81			`csrs mstatus, a0; \`
82
83	6	skordal	`#define RVTEST_FP_ENABLE \`
84	58	skordal	`li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \`
85			`csrs mstatus, a0; \`
86			`csrr a0, mcpuid; \`
87			`andi a0, a0, 1 << ('D' - 'A'); /* test for D extension */ \`
88			`bnez a0, 1f; \`
89			`RVTEST_PASS; /* "pass" the test if FPU not present */ \`
90			`1:csrwi fcsr, 0`
91	6	skordal
92			`#define RVTEST_VEC_ENABLE \`
93	58	skordal	`li a0, SSTATUS_XS & (SSTATUS_XS >> 1); \`
94			`csrs sstatus, a0; \`
95			`csrr a1, sstatus; \`
96	6	skordal	`and a0, a0, a1; \`
97			`bnez a0, 2f; \`
98			`RVTEST_PASS; \`
99			`2: \`
100
101			`#define RISCV_MULTICORE_DISABLE \`
102	58	skordal	`csrr a0, mhartid; \`
103			`1: bnez a0, 1b`
104	6	skordal
105	58	skordal	`#define EXTRA_TVEC_USER`
106			`#define EXTRA_TVEC_SUPERVISOR`
107			`#define EXTRA_TVEC_HYPERVISOR`
108			`#define EXTRA_TVEC_MACHINE`
109	6	skordal	`#define EXTRA_INIT`
110			`#define EXTRA_INIT_TIMER`
111
112			`#define RVTEST_CODE_BEGIN \`
113			`.text; \`
114	58	skordal	`.align 6; \`
115			`.weak stvec_handler; \`
116			`.weak mtvec_handler; \`
117			`tvec_user: \`
118			`EXTRA_TVEC_USER; \`
119			`/* test whether the test came from pass/fail */ \`
120			`la t5, ecall; \`
121			`csrr t6, mepc; \`
122			`beq t5, t6, write_tohost; \`
123			`/* test whether the stvec_handler target exists */ \`
124			`la t5, stvec_handler; \`
125			`bnez t5, mrts_routine; \`
126			`/* test whether the mtvec_handler target exists */ \`
127			`la t5, mtvec_handler; \`
128			`bnez t5, mtvec_handler; \`
129			`/* some other exception occurred */ \`
130			`j other_exception; \`
131			`.align 6; \`
132			`tvec_supervisor: \`
133			`EXTRA_TVEC_SUPERVISOR; \`
134			`csrr t5, mcause; \`
135			`bgez t5, tvec_user; \`
136			`mrts_routine: \`
137			`mrts; \`
138			`.align 6; \`
139			`tvec_hypervisor: \`
140			`EXTRA_TVEC_HYPERVISOR; \`
141			`/* renting some space out here */ \`
142			`other_exception: \`
143			`1: ori TESTNUM, TESTNUM, 1337; /* some other exception occurred */ \`
144			`write_tohost: \`
145			`csrw mtohost, TESTNUM; \`
146			`j write_tohost; \`
147			`.align 6; \`
148			`tvec_machine: \`
149			`EXTRA_TVEC_MACHINE; \`
150			`la t5, ecall; \`
151			`csrr t6, mepc; \`
152			`beq t5, t6, write_tohost; \`
153			`la t5, mtvec_handler; \`
154			`bnez t5, mtvec_handler; \`
155			`j other_exception; \`
156			`.align 6; \`
157			`.globl _start; \`
158	6	skordal	`_start: \`
159			`RISCV_MULTICORE_DISABLE; \`
160	58	skordal	`CHECK_XLEN; \`
161			`la t0, stvec_handler; \`
162			`csrw stvec, t0; \`
163			`li t0, MSTATUS_PRV1 \| MSTATUS_PRV2 \| MSTATUS_IE1 \| MSTATUS_IE2; \`
164			`csrc mstatus, t0; \`
165	6	skordal	`init; \`
166			`EXTRA_INIT; \`
167			`EXTRA_INIT_TIMER; \`
168	58	skordal	`la t0, 1f; \`
169			`csrw mepc, t0; \`
170			`csrr a0, mhartid; \`
171			`eret; \`
172			`1:`
173	6	skordal
174			`//-----------------------------------------------------------------------`
175			`// End Macro`
176			`//-----------------------------------------------------------------------`
177
178			`#define RVTEST_CODE_END \`
179	58	skordal	`ecall: ecall; \`
180			`j ecall`
181	6	skordal
182			`//-----------------------------------------------------------------------`
183			`// Pass/Fail Macro`
184			`//-----------------------------------------------------------------------`
185
186			`#define RVTEST_PASS \`
187			`fence; \`
188	58	skordal	`li TESTNUM, 1; \`
189			`j ecall`
190	6	skordal
191			`#define TESTNUM x28`
192			`#define RVTEST_FAIL \`
193			`fence; \`
194	58	skordal	`1: beqz TESTNUM, 1b; \`
195	6	skordal	`sll TESTNUM, TESTNUM, 1; \`
196			`or TESTNUM, TESTNUM, 1; \`
197	58	skordal	`j ecall`
198	6	skordal
199			`//-----------------------------------------------------------------------`
200			`// Data Section Macro`
201			`//-----------------------------------------------------------------------`
202
203			`#define EXTRA_DATA`
204
205			`#define RVTEST_DATA_BEGIN EXTRA_DATA .align 4; .global begin_signature; begin_signature:`
206			`#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:`
207
208			`#endif`

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[/] [potato/] [trunk/] [riscv-tests/] [riscv_test.h] - Blame information for rev 62