OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [riscv-tests/] [slti.S] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 skordal
# See LICENSE for license details.
2
 
3
#*****************************************************************************
4
# slti.S
5
#-----------------------------------------------------------------------------
6
#
7
# Test slti instruction.
8
#
9
 
10
#include "riscv_test.h"
11
#include "test_macros.h"
12
 
13
RVTEST_RV32U
14
RVTEST_CODE_BEGIN
15
 
16
  #-------------------------------------------------------------
17
  # Arithmetic tests
18
  #-------------------------------------------------------------
19
 
20
  TEST_IMM_OP( 2,  slti, 0, 0x00000000, 0x000 );
21
  TEST_IMM_OP( 3,  slti, 0, 0x00000001, 0x001 );
22
  TEST_IMM_OP( 4,  slti, 1, 0x00000003, 0x007 );
23
  TEST_IMM_OP( 5,  slti, 0, 0x00000007, 0x003 );
24
 
25
  TEST_IMM_OP( 6,  slti, 0, 0x00000000, 0x800 );
26
  TEST_IMM_OP( 7,  slti, 1, 0x80000000, 0x000 );
27
  TEST_IMM_OP( 8,  slti, 1, 0x80000000, 0x800 );
28
 
29
  TEST_IMM_OP( 9,  slti, 1, 0x00000000, 0x7ff );
30
  TEST_IMM_OP( 10, slti, 0, 0x7fffffff, 0x000 );
31
  TEST_IMM_OP( 11, slti, 0, 0x7fffffff, 0x7ff );
32
 
33
  TEST_IMM_OP( 12, slti, 1, 0x80000000, 0x7ff );
34
  TEST_IMM_OP( 13, slti, 0, 0x7fffffff, 0x800 );
35
 
36
  TEST_IMM_OP( 14, slti, 0, 0x00000000, 0xfff );
37
  TEST_IMM_OP( 15, slti, 1, 0xffffffff, 0x001 );
38
  TEST_IMM_OP( 16, slti, 0, 0xffffffff, 0xfff );
39
 
40
  #-------------------------------------------------------------
41
  # Source/Destination tests
42
  #-------------------------------------------------------------
43
 
44
  TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
45
 
46
  #-------------------------------------------------------------
47
  # Bypassing tests
48
  #-------------------------------------------------------------
49
 
50
  TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
51
  TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
52
  TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16,  9 );
53
 
54
  TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
55
  TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17,  8 );
56
  TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
57
 
58
  TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
59
  TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
60
 
61
  TEST_PASSFAIL
62
 
63
RVTEST_CODE_END
64
 
65
  .data
66
RVTEST_DATA_BEGIN
67
 
68
  TEST_DATA
69
 
70
RVTEST_DATA_END

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.