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[/] [potato/] [trunk/] [soc/] [pp_soc_7seg.vhd] - Blame information for rev 64

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-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity pp_soc_7seg is
        generic(
                NUM_DISPLAYS : natural := 8;             -- Number of 7-segment displays connected to the module.
                SWITCH_COUNT         : natural;          -- How many ticks of the input clock to count before switching displays.
                CATHODE_ENABLE_VALUE : std_logic := '0'; -- Value of the cathode output when enabled.
                ANODE_ENABLE_VALUE   : std_logic := '0'  -- Value of the anode output when enabled.
        );
        port(
                clk   : in std_logic;
                reset : in std_logic;
 
                -- Connections to the displays:
                seg7_anode   : out std_logic_vector(NUM_DISPLAYS - 1 downto 0); -- One for each display
                seg7_cathode : out std_logic_vector(6 downto 0);
 
                -- Wishbone interface:
                wb_adr_in  : in  std_logic_vector( 0 downto 0);
                wb_dat_in  : in  std_logic_vector(31 downto 0);
                wb_dat_out : out std_logic_vector(31 downto 0);
                wb_cyc_in  : in  std_logic;
                wb_stb_in  : in  std_logic;
                wb_we_in   : in  std_logic;
                wb_ack_out : out std_logic
        );
end entity pp_soc_7seg;
 
architecture behaviour of pp_soc_7seg is
        signal ctrl_value  : std_logic_vector(NUM_DISPLAYS * 4 - 1 downto 0);
        signal ctrl_enable : std_logic_vector(NUM_DISPLAYS - 1 downto 0);
 
        type seg7_array is array (0 to NUM_DISPLAYS - 1) of std_logic_vector(6 downto 0);
        signal output_array : seg7_array;
 
        subtype display_counter_type is natural range 0 to NUM_DISPLAYS - 1;
        signal active_display : display_counter_type := 0;
 
        constant ANODE_DISABLE_VALUE : std_logic := not ANODE_ENABLE_VALUE;
 
        subtype switch_counter_type is natural range 0 to SWITCH_COUNT - 1;
        signal switch_counter : switch_counter_type := 0;
 
        signal anodes : std_logic_vector(NUM_DISPLAYS - 1 downto 0);
 
        -- Wishbone controller acknowledge signal:
        signal ack : std_logic;
begin
 
        assert NUM_DISPLAYS <= 8 and NUM_DISPLAYS > 0
                report "Only 1 - 8 displays are supported by the 7-seg module!"
                severity FAILURE;
 
        -- Connect display outputs:
        seg7_cathode <= output_array(active_display) when CATHODE_ENABLE_VALUE = '0' else not output_array(active_display);
        seg7_anode <= anodes and not ctrl_enable when ANODE_ENABLE_VALUE = '1' else anodes and ctrl_enable;
 
        -- Create one decoder for each display:
        generate_decoders: for i in 0 to NUM_DISPLAYS - 1
        generate
                decoder: entity work.pp_seg7dec
                        port map(
                                input => ctrl_value(i * 4 + 3 downto i * 4),
                                output => output_array(i)
                        );
        end generate;
 
        -- Switch between the displays:
        switch_displays: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                anodes <= (0 => ANODE_ENABLE_VALUE, others => ANODE_DISABLE_VALUE);
                                active_display <= 0;
                        else
                                if switch_counter = SWITCH_COUNT - 1 then
                                        anodes <= std_logic_vector(rotate_left(unsigned(anodes), 1));
                                        switch_counter <= 0;
                                        if active_display = NUM_DISPLAYS - 1 then
                                                active_display <= 0;
                                        else
                                                active_display <= active_display + 1;
                                        end if;
                                else
                                        switch_counter <= switch_counter + 1;
                                end if;
                        end if;
                end if;
        end process switch_displays;
 
        ----- Wishbone controller: -----
        wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
        wishbone: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                ctrl_value <= (others => '0');
                                ctrl_enable <= (others => '1');
                                wb_dat_out <= (others => '0');
                                ack <= '0';
                        else
                                if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
                                        if wb_we_in = '1' then
                                                case wb_adr_in is
                                                        when b"0" =>
                                                                ctrl_enable <= wb_dat_in(NUM_DISPLAYS - 1 downto 0);
                                                        when b"1" =>
                                                                ctrl_value <= wb_dat_in(NUM_DISPLAYS * 4 - 1 downto 0);
                                                        when others =>
                                                end case;
                                                ack <= '1';
                                        else
                                                case wb_adr_in is
                                                        when b"0" =>
                                                                wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_enable), wb_dat_out'length));
                                                        when b"1" =>
                                                                wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_value), wb_dat_out'length));
                                                        when others =>
                                                end case;
                                                ack <= '1';
                                        end if;
                                elsif wb_stb_in = '0' then
                                        ack <= '0';
                                end if;
                        end if;
                end if;
        end process wishbone;
 
end architecture behaviour;

Line No.	Rev	Author	Line
1	61	skordal	`-- The Potato Processor - A simple processor for FPGAs`
2			`-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>`
3			`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.numeric_std.all;`
8
9			`entity pp_soc_7seg is`
10			`generic(`
11			`NUM_DISPLAYS : natural := 8; -- Number of 7-segment displays connected to the module.`
12			`SWITCH_COUNT : natural; -- How many ticks of the input clock to count before switching displays.`
13			`CATHODE_ENABLE_VALUE : std_logic := '0'; -- Value of the cathode output when enabled.`
14			`ANODE_ENABLE_VALUE : std_logic := '0' -- Value of the anode output when enabled.`
15			`);`
16			`port(`
17			`clk : in std_logic;`
18			`reset : in std_logic;`
19
20			`-- Connections to the displays:`
21			`seg7_anode : out std_logic_vector(NUM_DISPLAYS - 1 downto 0); -- One for each display`
22			`seg7_cathode : out std_logic_vector(6 downto 0);`
23
24			`-- Wishbone interface:`
25			`wb_adr_in : in std_logic_vector( 0 downto 0);`
26			`wb_dat_in : in std_logic_vector(31 downto 0);`
27			`wb_dat_out : out std_logic_vector(31 downto 0);`
28			`wb_cyc_in : in std_logic;`
29			`wb_stb_in : in std_logic;`
30			`wb_we_in : in std_logic;`
31			`wb_ack_out : out std_logic`
32			`);`
33			`end entity pp_soc_7seg;`
34
35			`architecture behaviour of pp_soc_7seg is`
36			`signal ctrl_value : std_logic_vector(NUM_DISPLAYS * 4 - 1 downto 0);`
37			`signal ctrl_enable : std_logic_vector(NUM_DISPLAYS - 1 downto 0);`
38
39			`type seg7_array is array (0 to NUM_DISPLAYS - 1) of std_logic_vector(6 downto 0);`
40			`signal output_array : seg7_array;`
41
42			`subtype display_counter_type is natural range 0 to NUM_DISPLAYS - 1;`
43			`signal active_display : display_counter_type := 0;`
44
45			`constant ANODE_DISABLE_VALUE : std_logic := not ANODE_ENABLE_VALUE;`
46
47			`subtype switch_counter_type is natural range 0 to SWITCH_COUNT - 1;`
48			`signal switch_counter : switch_counter_type := 0;`
49
50			`signal anodes : std_logic_vector(NUM_DISPLAYS - 1 downto 0);`
51
52			`-- Wishbone controller acknowledge signal:`
53			`signal ack : std_logic;`
54			`begin`
55
56			`assert NUM_DISPLAYS <= 8 and NUM_DISPLAYS > 0`
57			`report "Only 1 - 8 displays are supported by the 7-seg module!"`
58			`severity FAILURE;`
59
60			`-- Connect display outputs:`
61			`seg7_cathode <= output_array(active_display) when CATHODE_ENABLE_VALUE = '0' else not output_array(active_display);`
62	64	skordal	`seg7_anode <= anodes and not ctrl_enable when ANODE_ENABLE_VALUE = '1' else anodes and ctrl_enable;`
63	61	skordal
64			`-- Create one decoder for each display:`
65			`generate_decoders: for i in 0 to NUM_DISPLAYS - 1`
66			`generate`
67			`decoder: entity work.pp_seg7dec`
68			`port map(`
69			`input => ctrl_value(i * 4 + 3 downto i * 4),`
70			`output => output_array(i)`
71			`);`
72			`end generate;`
73
74			`-- Switch between the displays:`
75			`switch_displays: process(clk)`
76			`begin`
77			`if rising_edge(clk) then`
78			`if reset = '1' then`
79			`anodes <= (0 => ANODE_ENABLE_VALUE, others => ANODE_DISABLE_VALUE);`
80			`active_display <= 0;`
81			`else`
82			`if switch_counter = SWITCH_COUNT - 1 then`
83			`anodes <= std_logic_vector(rotate_left(unsigned(anodes), 1));`
84			`switch_counter <= 0;`
85			`if active_display = NUM_DISPLAYS - 1 then`
86			`active_display <= 0;`
87			`else`
88			`active_display <= active_display + 1;`
89			`end if;`
90			`else`
91			`switch_counter <= switch_counter + 1;`
92			`end if;`
93			`end if;`
94			`end if;`
95			`end process switch_displays;`
96
97			`----- Wishbone controller: -----`
98			`wb_ack_out <= ack and wb_cyc_in and wb_stb_in;`
99			`wishbone: process(clk)`
100			`begin`
101			`if rising_edge(clk) then`
102			`if reset = '1' then`
103			`ctrl_value <= (others => '0');`
104			`ctrl_enable <= (others => '1');`
105			`wb_dat_out <= (others => '0');`
106			`ack <= '0';`
107			`else`
108			`if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then`
109			`if wb_we_in = '1' then`
110			`case wb_adr_in is`
111			`when b"0" =>`
112			`ctrl_enable <= wb_dat_in(NUM_DISPLAYS - 1 downto 0);`
113			`when b"1" =>`
114			`ctrl_value <= wb_dat_in(NUM_DISPLAYS * 4 - 1 downto 0);`
115			`when others =>`
116			`end case;`
117			`ack <= '1';`
118			`else`
119			`case wb_adr_in is`
120			`when b"0" =>`
121			`wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_enable), wb_dat_out'length));`
122			`when b"1" =>`
123			`wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_value), wb_dat_out'length));`
124			`when others =>`
125			`end case;`
126			`ack <= '1';`
127			`end if;`
128			`elsif wb_stb_in = '0' then`
129			`ack <= '0';`
130			`end if;`
131			`end if;`
132			`end if;`
133			`end process wishbone;`
134
135			`end architecture behaviour;`

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[/] [potato/] [trunk/] [soc/] [pp_soc_7seg.vhd] - Blame information for rev 64