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skordal |
-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--! @brief Generic Wishbone GPIO Module.
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--! The following registers are defined:
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--! * 0: Input values, one bit per GPIO (read-only)
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--! * 1: Output values, one bit per GPIO (read/write)
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--! * 2: Direction register, 0 means input, 1 means output.
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entity pp_soc_gpio is
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generic(
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NUM_GPIOS : natural := 32
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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-- GPIO interface:
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gpio : inout std_logic_vector(NUM_GPIOS - 1 downto 0);
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-- Wishbone interface:
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wb_adr_in : in std_logic_vector( 1 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_we_in : in std_logic;
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wb_ack_out : out std_logic
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);
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end entity pp_soc_gpio;
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architecture behaviour of pp_soc_gpio is
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signal direction_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal output_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal input_register : std_logic_vector(NUM_GPIOS - 1 downto 0);
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signal ack : std_logic := '0';
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begin
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assert NUM_GPIOS > 0 and NUM_GPIOS <= 32
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report "Only a number between 1 and 32 (inclusive) GPIOs are supported!"
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severity FAILURE;
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io_setup: for i in 0 to NUM_GPIOS - 1 generate
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gpio(i) <= 'Z' when direction_register(i) = '0' else output_register(i);
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input_register(i) <= gpio(i) when direction_register(i) = '0' else '0';
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end generate;
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wishbone: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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direction_register <= (others => '0');
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output_register <= (others => '0');
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wb_dat_out <= (others => '0');
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ack <= '0';
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else
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if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
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if wb_we_in = '1' then
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case wb_adr_in is
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when b"01" =>
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output_register <= wb_dat_in(NUM_GPIOS - 1 downto 0);
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when b"10" =>
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direction_register <= wb_dat_in(NUM_GPIOS - 1 downto 0);
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when others =>
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end case;
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ack <= '1';
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else
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case wb_adr_in is
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when b"00" =>
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wb_dat_out <= std_logic_vector(resize(unsigned(input_register), wb_dat_out'length));
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when b"01" =>
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wb_dat_out <= std_logic_vector(resize(unsigned(output_register), wb_dat_out'length));
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when b"10" =>
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wb_dat_out <= std_logic_vector(resize(unsigned(direction_register), wb_dat_out'length));
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when others =>
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end case;
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ack <= '1';
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end if;
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elsif wb_stb_in = '0' then
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ack <= '0';
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end if;
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end if;
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end if;
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end process wishbone;
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end architecture behaviour;
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