OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [src/] [pp_comparator.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 skordal
-- The Potato Processor - A simple processor for FPGAs
2
-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
3 3 skordal
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
4 2 skordal
 
5
library ieee;
6
use ieee.std_logic_1164.all;
7
use ieee.numeric_std.all;
8
 
9
use work.pp_utilities.all;
10
 
11
--! @brief Component for comparing two registers in the ID stage whens branching.
12
entity pp_comparator is
13
        port(
14
                funct3   : in  std_logic_vector(14 downto 12);
15
                rs1, rs2 : in  std_logic_vector(31 downto 0);
16
                result   : out std_logic --! Result of the comparison.
17
        );
18
end entity pp_comparator;
19
 
20
architecture behaviour of pp_comparator is
21
begin
22
 
23
        compare: process(funct3, rs1, rs2)
24
        begin
25
                case funct3 is
26
                        when b"000" => -- EQ
27
                                result <= to_std_logic(rs1 = rs2);
28
                        when b"001" => -- NE
29
                                result <= to_std_logic(rs1 /= rs2);
30
                        when b"100" => -- LT
31
                                result <= to_std_logic(signed(rs1) < signed(rs2));
32
                        when b"101" => -- GE
33
                                result <= to_std_logic(signed(rs1) >= signed(rs2));
34
                        when b"110" => -- LTU
35
                                result <= to_std_logic(unsigned(rs1) < unsigned(rs2));
36
                        when b"111" => -- GEU
37
                                result <= to_std_logic(unsigned(rs1) >= unsigned(rs2));
38
                        when others =>
39
                                result <= '0';
40
                end case;
41
        end process compare;
42
 
43
end architecture behaviour;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.