OpenCores
URL https://opencores.org/ocsvn/potato/potato/trunk

Subversion Repositories potato

[/] [potato/] [trunk/] [src/] [pp_csr.vhd] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 skordal
-- The Potato Processor - A simple processor for FPGAs
2
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
3 3 skordal
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
4 2 skordal
 
5
library ieee;
6
use ieee.std_logic_1164.all;
7
 
8
--! @brief Package containing constants and utility functions relating to status and control registers.
9
package pp_csr is
10
 
11
        --! Type used for specifying control and status register addresses.
12
        subtype csr_address is std_logic_vector(11 downto 0);
13
 
14
        --! Type used for exception cause values.
15
        subtype csr_exception_cause is std_logic_vector(4 downto 0);
16
 
17
        function to_std_logic_vector(input : in csr_exception_cause) return std_logic_vector;
18
 
19
        --! Control/status register write mode:
20
        type csr_write_mode is (
21
                        CSR_WRITE_NONE, CSR_WRITE_SET, CSR_WRITE_CLEAR, CSR_WRITE_REPLACE
22
                );
23
 
24
        -- Exception cause values:
25
        constant CSR_CAUSE_INSTR_MISALIGN : csr_exception_cause := b"00000";
26
        constant CSR_CAUSE_INSTR_FETCH    : csr_exception_cause := b"00001";
27
        constant CSR_CAUSE_INVALID_INSTR  : csr_exception_cause := b"00010";
28
        constant CSR_CAUSE_SYSCALL        : csr_exception_cause := b"00110";
29
        constant CSR_CAUSE_BREAKPOINT     : csr_exception_cause := b"00111";
30
        constant CSR_CAUSE_LOAD_MISALIGN  : csr_exception_cause := b"01000";
31
        constant CSR_CAUSE_STORE_MISALIGN : csr_exception_cause := b"01001";
32
        constant CSR_CAUSE_LOAD_ERROR     : csr_exception_cause := b"01010";
33
        constant CSR_CAUSE_STORE_ERROR    : csr_exception_cause := b"01011";
34
        constant CSR_CAUSE_FROMHOST       : csr_exception_cause := b"11110";
35
        constant CSR_CAUSE_NONE           : csr_exception_cause := b"11111";
36
 
37
        constant CSR_CAUSE_IRQ_BASE       : csr_exception_cause := b"10000";
38
 
39
        -- Control register IDs, specified in the immediate of csr* instructions:
40
        constant CSR_STATUS   : csr_address := x"50a";
41
        constant CSR_HARTID   : csr_address := x"50b";
42
        constant CSR_SUP0     : csr_address := x"500";
43
        constant CSR_SUP1     : csr_address := x"501";
44
        constant CSR_BADVADDR : csr_address := x"503";
45
        constant CSR_TOHOST   : csr_address := x"51e";
46
        constant CSR_FROMHOST : csr_address := x"51f";
47
        constant CSR_CYCLE    : csr_address := x"c00";
48
        constant CSR_CYCLEH   : csr_address := x"c80";
49
        constant CSR_TIME     : csr_address := x"c01";
50
        constant CSR_TIMEH    : csr_address := x"c81";
51
        constant CSR_INSTRET  : csr_address := x"c02";
52
        constant CSR_INSTRETH : csr_address := x"c82";
53
        constant CSR_EPC      : csr_address := x"502";
54
        constant CSR_EVEC     : csr_address := x"508";
55
        constant CSR_CAUSE    : csr_address := x"509";
56
 
57
        -- Values used as control register IDs in SRET, SCALL and SBREAK:
58
        constant CSR_EPC_SRET   : csr_address := x"800";
59
 
60
        -- Status register bit indices:
61
        constant CSR_SR_S   : natural := 0;
62
        constant CSR_SR_PS  : natural := 1;
63
        constant CSR_SR_EI  : natural := 2;
64
        constant CSR_SR_PEI : natural := 3;
65
 
66
        -- Status register in Potato:
67
        -- * Bit 0, S: Supervisor mode, always 1
68
        -- * Bit 1, PS: Previous supervisor mode bit, always 1
69
        -- * Bit 2, EI: Enable interrupts bit
70
        -- * Bit 3, PEI: Previous enable interrupts bit
71
        -- * Bits 23 downto 16, IM: Interrupt mask
72
        -- * Bits 31 downto 24, PIM: Previous interrupt mask
73
 
74
        -- Status register record:
75
        type csr_status_register is
76
                record
77
                        ei, pei : std_logic;
78
                        im, pim : std_logic_vector(7 downto 0);
79
                end record;
80
 
81
        -- Exception context; this record contains all state that is stored
82
        -- when an exception is taken.
83
        type csr_exception_context is
84
                record
85
                        status   : csr_status_register;
86
                        cause    : csr_exception_cause;
87
                        badvaddr : std_logic_vector(31 downto 0);
88
                end record;
89
 
90
        -- Reset value of the status register:
91
        constant CSR_SR_DEFAULT : csr_status_register := (ei => '0', pei => '0', im => x"00", pim => x"00");
92
 
93
        -- Converts a status register record into an std_logic_vector:
94
        function to_std_logic_vector(input : in csr_status_register)
95
                return std_logic_vector;
96
 
97
        -- Converts an std_logic_vector into a status register record:
98
        function to_csr_status_register(input : in std_logic_vector(31 downto 0))
99
                return csr_status_register;
100
 
101
        --! Checks if a control register is writeable.
102
        function csr_is_writeable(csr : in csr_address) return boolean;
103
 
104
end package pp_csr;
105
 
106
package body pp_csr is
107
 
108
        function to_std_logic_vector(input : in csr_exception_cause)
109
                return std_logic_vector is
110
        begin
111
                return (31 downto 5 => '0') & input;
112
        end function to_std_logic_vector;
113
 
114
        function to_std_logic_vector(input : in csr_status_register)
115
                return std_logic_vector is
116
        begin
117
                return input.pim & input.im & (15 downto 4 => '0') & input.pei & input.ei & '1' & '1';
118
        end function to_std_logic_vector;
119
 
120
        function to_csr_status_register(input : in std_logic_vector(31 downto 0))
121
                return csr_status_register
122
        is
123
                variable retval : csr_status_register;
124
        begin
125
                retval.ei  := input(CSR_SR_EI);
126
                retval.pei := input(CSR_SR_PEI);
127
                retval.im  := input(23 downto 16);
128
                retval.pim := input(31 downto 24);
129
                return retval;
130
        end function to_csr_status_register;
131
 
132
        function csr_is_writeable(csr : in csr_address) return boolean is
133
        begin
134
                case csr is
135
                        when CSR_FROMHOST | CSR_CYCLE | CSR_CYCLEH | CSR_HARTID
136
                                        | CSR_TIME | CSR_TIMEH | CSR_INSTRET | CSR_INSTRETH
137
                                        | CSR_CAUSE | CSR_BADVADDR =>
138
                                return false;
139
                        when others =>
140
                                return true;
141
                end case;
142
        end function csr_is_writeable;
143
 
144
end package body pp_csr;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.