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-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.pp_types.all;
use work.pp_csr.all;
use work.pp_utilities.all;
 
entity pp_execute is
        port(
                clk    : in std_logic;
                reset  : in std_logic;
 
                stall, flush : in std_logic;
 
                -- Interrupt inputs:
                irq : in std_logic_vector(7 downto 0);
                software_interrupt, timer_interrupt : in std_logic;
 
                -- Data memory outputs:
                dmem_address   : out std_logic_vector(31 downto 0);
                dmem_data_out  : out std_logic_vector(31 downto 0);
                dmem_data_size : out std_logic_vector( 1 downto 0);
                dmem_read_req  : out std_logic;
                dmem_write_req : out std_logic;
 
                -- Register addresses:
                rs1_addr_in, rs2_addr_in, rd_addr_in : in  register_address;
                rd_addr_out                          : out register_address;
 
                -- Register values:
                rs1_data_in, rs2_data_in : in std_logic_vector(31 downto 0);
                rd_data_out              : out std_logic_vector(31 downto 0);
 
                -- Constant values:
                shamt_in     : in std_logic_vector(4 downto 0);
                immediate_in : in std_logic_vector(31 downto 0);
 
                -- Instruction address:
                pc_in     : in  std_logic_vector(31 downto 0);
                pc_out    : out std_logic_vector(31 downto 0);
 
                -- Funct3 value from the instruction, used to choose which comparison
                -- is used when branching:
                funct3_in : in std_logic_vector(2 downto 0);
 
                -- CSR signals:
                csr_addr_in          : in  csr_address;
                csr_addr_out         : out csr_address;
                csr_write_in         : in  csr_write_mode;
                csr_write_out        : out csr_write_mode;
                csr_value_in         : in  std_logic_vector(31 downto 0);
                csr_value_out        : out std_logic_vector(31 downto 0);
                csr_writeable_in     : in  boolean;
                csr_use_immediate_in : in  std_logic;
 
                -- Control signals:
                alu_op_in    : in  alu_operation;
                alu_x_src_in : in  alu_operand_source;
                alu_y_src_in : in  alu_operand_source;
                rd_write_in  : in  std_logic;
                rd_write_out : out std_logic;
                branch_in    : in  branch_type;
                branch_out   : out branch_type;
 
                -- Memory control signals:
                mem_op_in    : in  memory_operation_type;
                mem_op_out   : out memory_operation_type;
                mem_size_in  : in  memory_operation_size;
                mem_size_out : out memory_operation_size;
 
                -- Whether the instruction should be counted:
                count_instruction_in  : in  std_logic;
                count_instruction_out : out std_logic;
 
                -- Exception control registers:
                ie_in, ie1_in : in  std_logic;
                mie_in        : in  std_logic_vector(31 downto 0);
                mtvec_in      : in  std_logic_vector(31 downto 0);
                mtvec_out     : out std_logic_vector(31 downto 0);
                --mepc_in       : in  std_logic_vector(31 downto 0);
 
                -- Exception signals:
                decode_exception_in       : in std_logic;
                decode_exception_cause_in : in csr_exception_cause;
 
                -- Exception outputs:
                exception_out         : out std_logic;
                exception_context_out : out csr_exception_context;
 
                -- Control outputs:
                jump_out        : out std_logic;
                jump_target_out : out std_logic_vector(31 downto 0);
 
                -- Inputs to the forwarding logic from the MEM stage:
                mem_rd_write          : in std_logic;
                mem_rd_addr           : in register_address;
                mem_rd_value          : in std_logic_vector(31 downto 0);
                mem_csr_addr          : in csr_address;
                mem_csr_write         : in csr_write_mode;
                mem_csr_value         : in std_logic_vector(31 downto 0);
                mem_exception         : in std_logic;
                mem_exception_context : in csr_exception_context;
 
                -- Inputs to the forwarding logic from the WB stage:
                wb_rd_write          : in std_logic;
                wb_rd_addr           : in register_address;
                wb_rd_value          : in std_logic_vector(31 downto 0);
                wb_csr_addr          : in csr_address;
                wb_csr_write         : in csr_write_mode;
                wb_csr_value         : in std_logic_vector(31 downto 0);
                wb_exception         : in std_logic;
                wb_exception_context : in csr_exception_context;
 
                -- Hazard detection unit signals:
                mem_mem_op : in memory_operation_type;
                hazard_detected : out std_logic
        );
end entity pp_execute;
 
architecture behaviour of pp_execute is
        signal alu_op : alu_operation;
        signal alu_x_src, alu_y_src : alu_operand_source;
 
        signal alu_x, alu_y, alu_result : std_logic_vector(31 downto 0);
 
        signal rs1_addr, rs2_addr : register_address;
        signal rs1_data, rs2_data : std_logic_vector(31 downto 0);
 
        signal mem_op : memory_operation_type;
        signal mem_size : memory_operation_size;
 
        signal pc        : std_logic_vector(31 downto 0);
        signal immediate : std_logic_vector(31 downto 0);
        signal shamt     : std_logic_vector( 4 downto 0);
        signal funct3    : std_logic_vector( 2 downto 0);
 
        signal rs1_forwarded, rs2_forwarded : std_logic_vector(31 downto 0);
 
        signal branch : branch_type;
        signal branch_condition : std_logic;
        signal do_jump : std_logic;
        signal jump_target : std_logic_vector(31 downto 0);
 
        signal mtvec, mtvec_forwarded : std_logic_vector(31 downto 0);
        signal mie, mie_forwarded : std_logic_vector(31 downto 0);
 
        signal csr_write : csr_write_mode;
        signal csr_addr  : csr_address;
        signal csr_use_immediate : std_logic;
        signal csr_writeable : boolean;
 
        signal csr_value, csr_value_forwarded : std_logic_vector(31 downto 0);
 
        signal decode_exception : std_logic;
        signal decode_exception_cause : csr_exception_cause;
 
        signal exception_taken : std_logic;
        signal exception_cause : csr_exception_cause;
        signal exception_addr  : std_logic_vector(31 downto 0);
 
        signal exception_context_forwarded : csr_exception_context;
 
        signal data_misaligned, instr_misaligned : std_logic;
 
        signal irq_asserted : std_logic;
        signal irq_asserted_num : std_logic_vector(3 downto 0);
begin
 
        -- Register values should not be latched in by a clocked process,
        -- this is already done in the register files.
        csr_value <= csr_value_in;
        rd_data_out <= alu_result;
 
        branch_out <= branch;
 
        mem_op_out <= mem_op;
        mem_size_out <= mem_size;
 
        csr_write_out <= csr_write;
        csr_addr_out  <= csr_addr;
 
        pc_out <= pc;
 
        exception_out <= exception_taken;
        exception_context_out <= (
                                ie => exception_context_forwarded.ie,
                                ie1 => exception_context_forwarded.ie1,
                                cause => exception_cause,
                                badaddr => exception_addr
                        ) when exception_taken = '1' else exception_context_forwarded;
 
        do_jump <= (to_std_logic(branch = BRANCH_JUMP or branch = BRANCH_JUMP_INDIRECT)
                or (to_std_logic(branch = BRANCH_CONDITIONAL) and branch_condition)
                or to_std_logic(branch = BRANCH_SRET)) and not stall;
        jump_out <= do_jump;
        jump_target_out <= jump_target;
 
        mtvec_out <= std_logic_vector(unsigned(mtvec_forwarded) + CSR_MTVEC_M_OFFSET);
        exception_taken <= not stall and (decode_exception or to_std_logic(exception_cause /= CSR_CAUSE_NONE));
 
        irq_asserted <= to_std_logic(exception_context_forwarded.ie = '1' and (irq and mie_forwarded(31 downto 24)) /= x"00");
 
        rs1_data <= rs1_data_in;
        rs2_data <= rs2_data_in;
 
        dmem_address <= alu_result when (mem_op /= MEMOP_TYPE_NONE and mem_op /= MEMOP_TYPE_INVALID) and exception_taken = '0'
                else (others => '0');
        dmem_data_out <= rs2_forwarded;
        dmem_write_req <= '1' when mem_op = MEMOP_TYPE_STORE and exception_taken = '0' else '0';
        dmem_read_req <= '1' when memop_is_load(mem_op) and exception_taken = '0' else '0';
 
        pipeline_register: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' or flush = '1' then
                                rd_write_out <= '0';
                                branch <= BRANCH_NONE;
                                csr_write <= CSR_WRITE_NONE;
                                mem_op <= MEMOP_TYPE_NONE;
                                decode_exception <= '0';
                                count_instruction_out <= '0';
                        elsif stall = '0' then
                                pc <= pc_in;
                                count_instruction_out <= count_instruction_in;
 
                                -- Register signals:
                                rd_write_out <= rd_write_in;
                                rd_addr_out <= rd_addr_in;
                                rs1_addr <= rs1_addr_in;
                                rs2_addr <= rs2_addr_in;
 
                                -- ALU signals:
                                alu_op <= alu_op_in;
                                alu_x_src <= alu_x_src_in;
                                alu_y_src <= alu_y_src_in;
 
                                -- Control signals:
                                branch <= branch_in;
                                mem_op <= mem_op_in;
                                mem_size <= mem_size_in;
 
                                -- Constant values:
                                immediate <= immediate_in;
                                shamt <= shamt_in;
                                funct3 <= funct3_in;
 
                                -- CSR signals:
                                csr_write <= csr_write_in;
                                csr_addr <= csr_addr_in;
                                csr_use_immediate <= csr_use_immediate_in;
                                csr_writeable <= csr_writeable_in;
 
                                -- Exception vector base:
                                mtvec <= mtvec_in;
                                mie <= mie_in;
 
                                -- Instruction decoder exceptions:
                                decode_exception <= decode_exception_in;
                                decode_exception_cause <= decode_exception_cause_in;
                        end if;
                end if;
        end process pipeline_register;
 
        set_data_size: process(mem_size)
        begin
                case mem_size is
                        when MEMOP_SIZE_BYTE =>
                                dmem_data_size <= b"01";
                        when MEMOP_SIZE_HALFWORD =>
                                dmem_data_size <= b"10";
                        when MEMOP_SIZE_WORD =>
                                dmem_data_size <= b"00";
                        when others =>
                                dmem_data_size <= b"11";
                end case;
        end process set_data_size;
 
        get_irq_num: process(irq, exception_context_forwarded, mie_forwarded)
                variable temp : std_logic_vector(3 downto 0);
        begin
                temp := (others => '0');
 
                for i in 0 to 7 loop
                        if irq(i) = '1' and mie_forwarded(24 + i) = '1' then
                                temp := std_logic_vector(to_unsigned(i, temp'length));
                                exit;
                        end if;
                end loop;
 
                irq_asserted_num <= temp;
        end process get_irq_num;
 
        data_misalign_check: process(mem_size, alu_result)
        begin
                case mem_size is
                        when MEMOP_SIZE_HALFWORD =>
                                if alu_result(0) /= '0' then
                                        data_misaligned <= '1';
                                else
                                        data_misaligned <= '0';
                                end if;
                        when MEMOP_SIZE_WORD =>
                                if alu_result(1 downto 0) /= b"00" then
                                        data_misaligned <= '1';
                                else
                                        data_misaligned <= '0';
                                end if;
                        when others =>
                                data_misaligned <= '0';
                end case;
        end process data_misalign_check;
 
        instr_misalign_check: process(jump_target, branch, branch_condition, do_jump)
        begin
                if jump_target(1 downto 0) /= b"00" and do_jump = '1' then
                        instr_misaligned <= '1';
                else
                        instr_misaligned <= '0';
                end if;
        end process instr_misalign_check;
 
        find_exception_cause: process(decode_exception, decode_exception_cause, mem_op,
                data_misaligned, instr_misaligned, irq_asserted, irq_asserted_num, mie_forwarded,
                software_interrupt, timer_interrupt, exception_context_forwarded)
        begin
                if irq_asserted = '1' then
                        exception_cause <= std_logic_vector(unsigned(CSR_CAUSE_IRQ_BASE) + unsigned(irq_asserted_num));
                elsif software_interrupt = '1' and mie_forwarded(CSR_MIE_MSIE) = '1' and exception_context_forwarded.ie = '1' then
                        exception_cause <= CSR_CAUSE_SOFTWARE_INT;
                elsif timer_interrupt = '1' and mie_forwarded(CSR_MIE_MTIE) = '1' and exception_context_forwarded.ie = '1' then
                        exception_cause <= CSR_CAUSE_TIMER_INT;
                elsif decode_exception = '1' then
                        exception_cause <= decode_exception_cause;
                elsif mem_op = MEMOP_TYPE_INVALID then
                        exception_cause <= CSR_CAUSE_INVALID_INSTR;
                elsif instr_misaligned = '1' then
                        exception_cause <= CSR_CAUSE_INSTR_MISALIGN;
                elsif data_misaligned = '1' and mem_op = MEMOP_TYPE_STORE then
                        exception_cause <= CSR_CAUSE_STORE_MISALIGN;
                elsif data_misaligned = '1' and memop_is_load(mem_op) then
                        exception_cause <= CSR_CAUSE_LOAD_MISALIGN;
                else
                        exception_cause <= CSR_CAUSE_NONE;
                end if;
        end process find_exception_cause;
 
        find_exception_addr: process(instr_misaligned, data_misaligned, jump_target, alu_result)
        begin
                if instr_misaligned = '1' then
                        exception_addr <= jump_target;
                elsif data_misaligned = '1' then
                        exception_addr <= alu_result;
                else
                        exception_addr <= (others => '0');
                end if;
        end process find_exception_addr;
 
        calc_jump_tgt: process(branch, pc, rs1_forwarded, immediate, csr_value_forwarded)
        begin
                case branch is
                        when BRANCH_JUMP | BRANCH_CONDITIONAL =>
                                jump_target <= std_logic_vector(unsigned(pc) + unsigned(immediate));
                        when BRANCH_JUMP_INDIRECT =>
                                jump_target <= std_logic_vector(unsigned(rs1_forwarded) + unsigned(immediate));
                        when BRANCH_SRET =>
                                jump_target <= csr_value_forwarded;
                        when others =>
                                jump_target <= (others => '0');
                end case;
        end process calc_jump_tgt;
 
        alu_x_mux: entity work.pp_alu_mux
                port map(
                        source => alu_x_src,
                        register_value => rs1_forwarded,
                        immediate_value => immediate,
                        shamt_value => shamt,
                        pc_value => pc,
                        csr_value => csr_value_forwarded,
                        output => alu_x
                );
 
        alu_y_mux: entity work.pp_alu_mux
                port map(
                        source => alu_y_src,
                        register_value => rs2_forwarded,
                        immediate_value => immediate,
                        shamt_value => shamt,
                        pc_value => pc,
                        csr_value => csr_value_forwarded,
                        output => alu_y
                );
 
        alu_x_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs1_addr,
                rs1_data, wb_rd_write, wb_rd_addr, wb_rd_value)
        begin
                if mem_rd_write = '1' and mem_rd_addr = rs1_addr and mem_rd_addr /= b"00000" then
                        rs1_forwarded <= mem_rd_value;
                elsif wb_rd_write = '1' and wb_rd_addr = rs1_addr and wb_rd_addr /= b"00000" then
                        rs1_forwarded <= wb_rd_value;
                else
                        rs1_forwarded <= rs1_data;
                end if;
        end process alu_x_forward;
 
        alu_y_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs2_addr,
                rs2_data, wb_rd_write, wb_rd_addr, wb_rd_value)
        begin
                if mem_rd_write = '1' and mem_rd_addr = rs2_addr and mem_rd_addr /= b"00000" then
                        rs2_forwarded <= mem_rd_value;
                elsif wb_rd_write = '1' and wb_rd_addr = rs2_addr and wb_rd_addr /= b"00000" then
                        rs2_forwarded <= wb_rd_value;
                else
                        rs2_forwarded <= rs2_data;
                end if;
        end process alu_y_forward;
 
        csr_forward: process(mem_csr_write, wb_csr_write, csr_addr, mem_csr_addr, wb_csr_addr,
                csr_value, mem_csr_value, wb_csr_value, csr_writeable, mem_exception, wb_exception,
                mem_exception_context, wb_exception_context)
        begin
                if csr_addr = CSR_MCAUSE and mem_exception = '1' then
                        csr_value_forwarded <= to_std_logic_vector(mem_exception_context.cause);
                elsif csr_addr = CSR_MSTATUS and mem_exception = '1' then
                        csr_value_forwarded <= csr_make_mstatus(mem_exception_context.ie, mem_exception_context.ie1);
                elsif csr_addr = CSR_MBADADDR and mem_exception = '1' then
                        csr_value_forwarded <= mem_exception_context.badaddr;
                elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = csr_addr and csr_writeable then
                        csr_value_forwarded <= mem_csr_value;
                elsif csr_addr = CSR_MCAUSE and wb_exception = '1' then
                        csr_value_forwarded <= to_std_logic_vector(wb_exception_context.cause);
                elsif csr_addr = CSR_MSTATUS and wb_exception = '1' then
                        csr_value_forwarded <= csr_make_mstatus(wb_exception_context.ie, wb_exception_context.ie1);
                elsif csr_addr = CSR_MBADADDR and wb_exception = '1' then
                        csr_value_forwarded <= wb_exception_context.badaddr;
                elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = csr_addr and csr_writeable then
                        csr_value_forwarded <= wb_csr_value;
                else
                        csr_value_forwarded <= csr_value;
                end if;
        end process csr_forward;
 
        mtvec_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,
                wb_csr_write, wb_csr_addr, wb_csr_value, mtvec)
        begin
                if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MTVEC then
                        mtvec_forwarded <= mem_csr_value;
                elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MTVEC then
                        mtvec_forwarded <= wb_csr_value;
                else
                        mtvec_forwarded <= mtvec;
                end if;
        end process mtvec_forward;
 
        mie_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,
                wb_csr_write, wb_csr_addr, wb_csr_value, mie)
        begin
                if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MIE then
                        mie_forwarded <= mem_csr_value;
                elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MIE then
                        mie_forwarded <= wb_csr_value;
                else
                        mie_forwarded <= mie;
                end if;
        end process mie_forward;
 
        exception_ctx_forward: process(mem_exception, wb_exception, mem_exception_context, wb_exception_context,
                exception_cause, exception_addr, mem_csr_write, mem_csr_addr, mem_csr_value,
                wb_csr_write, wb_csr_addr, wb_csr_value, ie_in, ie1_in)
        begin
                if mem_exception = '1' then
                        exception_context_forwarded <= mem_exception_context;
                elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MSTATUS then
                        exception_context_forwarded <= (
                                ie => mem_csr_value(CSR_SR_IE),
                                ie1 => mem_csr_value(CSR_SR_IE1),
                                cause => exception_cause,
                                badaddr => exception_addr);
                elsif wb_exception = '1' then
                        exception_context_forwarded <= wb_exception_context;
                elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MSTATUS then
                        exception_context_forwarded <= (
                                ie => wb_csr_value(CSR_SR_IE),
                                ie1 => wb_csr_value(CSR_SR_IE1),
                                cause => exception_cause,
                                badaddr => exception_addr);
                else
                        exception_context_forwarded.ie <= ie_in;
                        exception_context_forwarded.ie1 <= ie1_in;
                        exception_context_forwarded.cause <= exception_cause;
                        exception_context_forwarded.badaddr <= exception_addr;
                end if;
        end process exception_ctx_forward;
 
        detect_load_hazard: process(mem_mem_op, mem_rd_addr, rs1_addr, rs2_addr,
                alu_x_src, alu_y_src)
        begin
                if (mem_mem_op = MEMOP_TYPE_LOAD or mem_mem_op = MEMOP_TYPE_LOAD_UNSIGNED) and
                                ((alu_x_src = ALU_SRC_REG and mem_rd_addr = rs1_addr and rs1_addr /= b"00000")
                        or
                                (alu_y_src = ALU_SRC_REG and mem_rd_addr = rs2_addr and rs2_addr /= b"00000"))
                then
                        hazard_detected <= '1';
                else
                        hazard_detected <= '0';
                end if;
        end process detect_load_hazard;
 
        branch_comparator: entity work.pp_comparator
                port map(
                        funct3 => funct3,
                        rs1 => rs1_forwarded,
                        rs2 => rs2_forwarded,
                        result => branch_condition
                );
 
        alu_instance: entity work.pp_alu
                port map(
                        result => alu_result,
                        x => alu_x,
                        y => alu_y,
                        operation => alu_op
                );
 
        csr_alu_instance: entity work.pp_csr_alu
                port map(
                        x => csr_value_forwarded,
                        y => rs1_forwarded,
                        result => csr_value_out,
                        immediate => rs1_addr,
                        use_immediate => csr_use_immediate,
                        write_mode => csr_write
                );
 
 
end architecture behaviour;

Line No.	Rev	Author	Line
1	2	skordal	`-- The Potato Processor - A simple processor for FPGAs`
2			`-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>`
3	3	skordal	`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4	2	skordal
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7			`use ieee.numeric_std.all;`
8
9			`use work.pp_types.all;`
10			`use work.pp_csr.all;`
11			`use work.pp_utilities.all;`
12
13			`entity pp_execute is`
14			`port(`
15			`clk : in std_logic;`
16			`reset : in std_logic;`
17
18			`stall, flush : in std_logic;`
19
20	58	skordal	`-- Interrupt inputs:`
21	2	skordal	`irq : in std_logic_vector(7 downto 0);`
22	58	skordal	`software_interrupt, timer_interrupt : in std_logic;`
23	2	skordal
24			`-- Data memory outputs:`
25			`dmem_address : out std_logic_vector(31 downto 0);`
26			`dmem_data_out : out std_logic_vector(31 downto 0);`
27			`dmem_data_size : out std_logic_vector( 1 downto 0);`
28			`dmem_read_req : out std_logic;`
29			`dmem_write_req : out std_logic;`
30
31			`-- Register addresses:`
32			`rs1_addr_in, rs2_addr_in, rd_addr_in : in register_address;`
33			`rd_addr_out : out register_address;`
34
35			`-- Register values:`
36			`rs1_data_in, rs2_data_in : in std_logic_vector(31 downto 0);`
37			`rd_data_out : out std_logic_vector(31 downto 0);`
38
39			`-- Constant values:`
40			`shamt_in : in std_logic_vector(4 downto 0);`
41			`immediate_in : in std_logic_vector(31 downto 0);`
42
43			`-- Instruction address:`
44			`pc_in : in std_logic_vector(31 downto 0);`
45			`pc_out : out std_logic_vector(31 downto 0);`
46
47			`-- Funct3 value from the instruction, used to choose which comparison`
48			`-- is used when branching:`
49			`funct3_in : in std_logic_vector(2 downto 0);`
50
51			`-- CSR signals:`
52			`csr_addr_in : in csr_address;`
53			`csr_addr_out : out csr_address;`
54			`csr_write_in : in csr_write_mode;`
55			`csr_write_out : out csr_write_mode;`
56			`csr_value_in : in std_logic_vector(31 downto 0);`
57			`csr_value_out : out std_logic_vector(31 downto 0);`
58			`csr_writeable_in : in boolean;`
59			`csr_use_immediate_in : in std_logic;`
60
61			`-- Control signals:`
62			`alu_op_in : in alu_operation;`
63			`alu_x_src_in : in alu_operand_source;`
64			`alu_y_src_in : in alu_operand_source;`
65			`rd_write_in : in std_logic;`
66			`rd_write_out : out std_logic;`
67			`branch_in : in branch_type;`
68			`branch_out : out branch_type;`
69
70			`-- Memory control signals:`
71			`mem_op_in : in memory_operation_type;`
72			`mem_op_out : out memory_operation_type;`
73			`mem_size_in : in memory_operation_size;`
74			`mem_size_out : out memory_operation_size;`
75
76			`-- Whether the instruction should be counted:`
77			`count_instruction_in : in std_logic;`
78			`count_instruction_out : out std_logic;`
79
80			`-- Exception control registers:`
81	58	skordal	`ie_in, ie1_in : in std_logic;`
82			`mie_in : in std_logic_vector(31 downto 0);`
83			`mtvec_in : in std_logic_vector(31 downto 0);`
84			`mtvec_out : out std_logic_vector(31 downto 0);`
85			`--mepc_in : in std_logic_vector(31 downto 0);`
86	2	skordal
87			`-- Exception signals:`
88			`decode_exception_in : in std_logic;`
89			`decode_exception_cause_in : in csr_exception_cause;`
90
91			`-- Exception outputs:`
92			`exception_out : out std_logic;`
93			`exception_context_out : out csr_exception_context;`
94
95			`-- Control outputs:`
96			`jump_out : out std_logic;`
97			`jump_target_out : out std_logic_vector(31 downto 0);`
98
99			`-- Inputs to the forwarding logic from the MEM stage:`
100			`mem_rd_write : in std_logic;`
101			`mem_rd_addr : in register_address;`
102			`mem_rd_value : in std_logic_vector(31 downto 0);`
103			`mem_csr_addr : in csr_address;`
104			`mem_csr_write : in csr_write_mode;`
105			`mem_csr_value : in std_logic_vector(31 downto 0);`
106			`mem_exception : in std_logic;`
107			`mem_exception_context : in csr_exception_context;`
108
109			`-- Inputs to the forwarding logic from the WB stage:`
110			`wb_rd_write : in std_logic;`
111			`wb_rd_addr : in register_address;`
112			`wb_rd_value : in std_logic_vector(31 downto 0);`
113			`wb_csr_addr : in csr_address;`
114			`wb_csr_write : in csr_write_mode;`
115			`wb_csr_value : in std_logic_vector(31 downto 0);`
116			`wb_exception : in std_logic;`
117			`wb_exception_context : in csr_exception_context;`
118
119			`-- Hazard detection unit signals:`
120			`mem_mem_op : in memory_operation_type;`
121			`hazard_detected : out std_logic`
122			`);`
123			`end entity pp_execute;`
124
125			`architecture behaviour of pp_execute is`
126			`signal alu_op : alu_operation;`
127			`signal alu_x_src, alu_y_src : alu_operand_source;`
128
129			`signal alu_x, alu_y, alu_result : std_logic_vector(31 downto 0);`
130
131			`signal rs1_addr, rs2_addr : register_address;`
132			`signal rs1_data, rs2_data : std_logic_vector(31 downto 0);`
133
134			`signal mem_op : memory_operation_type;`
135			`signal mem_size : memory_operation_size;`
136
137			`signal pc : std_logic_vector(31 downto 0);`
138			`signal immediate : std_logic_vector(31 downto 0);`
139			`signal shamt : std_logic_vector( 4 downto 0);`
140			`signal funct3 : std_logic_vector( 2 downto 0);`
141
142			`signal rs1_forwarded, rs2_forwarded : std_logic_vector(31 downto 0);`
143
144			`signal branch : branch_type;`
145			`signal branch_condition : std_logic;`
146	17	skordal	`signal do_jump : std_logic;`
147	2	skordal	`signal jump_target : std_logic_vector(31 downto 0);`
148
149	58	skordal	`signal mtvec, mtvec_forwarded : std_logic_vector(31 downto 0);`
150			`signal mie, mie_forwarded : std_logic_vector(31 downto 0);`
151	2	skordal
152			`signal csr_write : csr_write_mode;`
153			`signal csr_addr : csr_address;`
154			`signal csr_use_immediate : std_logic;`
155			`signal csr_writeable : boolean;`
156
157			`signal csr_value, csr_value_forwarded : std_logic_vector(31 downto 0);`
158
159			`signal decode_exception : std_logic;`
160			`signal decode_exception_cause : csr_exception_cause;`
161
162			`signal exception_taken : std_logic;`
163			`signal exception_cause : csr_exception_cause;`
164	58	skordal	`signal exception_addr : std_logic_vector(31 downto 0);`
165	2	skordal
166			`signal exception_context_forwarded : csr_exception_context;`
167
168			`signal data_misaligned, instr_misaligned : std_logic;`
169
170			`signal irq_asserted : std_logic;`
171			`signal irq_asserted_num : std_logic_vector(3 downto 0);`
172			`begin`
173
174			`-- Register values should not be latched in by a clocked process,`
175			`-- this is already done in the register files.`
176			`csr_value <= csr_value_in;`
177			`rd_data_out <= alu_result;`
178
179			`branch_out <= branch;`
180
181			`mem_op_out <= mem_op;`
182			`mem_size_out <= mem_size;`
183
184			`csr_write_out <= csr_write;`
185			`csr_addr_out <= csr_addr;`
186
187			`pc_out <= pc;`
188
189			`exception_out <= exception_taken;`
190			`exception_context_out <= (`
191	58	skordal	`ie => exception_context_forwarded.ie,`
192			`ie1 => exception_context_forwarded.ie1,`
193	2	skordal	`cause => exception_cause,`
194	58	skordal	`badaddr => exception_addr`
195	2	skordal	`) when exception_taken = '1' else exception_context_forwarded;`
196
197	35	skordal	`do_jump <= (to_std_logic(branch = BRANCH_JUMP or branch = BRANCH_JUMP_INDIRECT)`
198	2	skordal	`or (to_std_logic(branch = BRANCH_CONDITIONAL) and branch_condition)`
199	35	skordal	`or to_std_logic(branch = BRANCH_SRET)) and not stall;`
200	17	skordal	`jump_out <= do_jump;`
201	2	skordal	`jump_target_out <= jump_target;`
202
203	58	skordal	`mtvec_out <= std_logic_vector(unsigned(mtvec_forwarded) + CSR_MTVEC_M_OFFSET);`
204			`exception_taken <= not stall and (decode_exception or to_std_logic(exception_cause /= CSR_CAUSE_NONE));`
205	2	skordal
206	58	skordal	`irq_asserted <= to_std_logic(exception_context_forwarded.ie = '1' and (irq and mie_forwarded(31 downto 24)) /= x"00");`
207	2	skordal
208			`rs1_data <= rs1_data_in;`
209			`rs2_data <= rs2_data_in;`
210
211	58	skordal	`dmem_address <= alu_result when (mem_op /= MEMOP_TYPE_NONE and mem_op /= MEMOP_TYPE_INVALID) and exception_taken = '0'`
212			`else (others => '0');`
213	2	skordal	`dmem_data_out <= rs2_forwarded;`
214	58	skordal	`dmem_write_req <= '1' when mem_op = MEMOP_TYPE_STORE and exception_taken = '0' else '0';`
215			`dmem_read_req <= '1' when memop_is_load(mem_op) and exception_taken = '0' else '0';`
216	2	skordal
217			`pipeline_register: process(clk)`
218			`begin`
219			`if rising_edge(clk) then`
220			`if reset = '1' or flush = '1' then`
221			`rd_write_out <= '0';`
222			`branch <= BRANCH_NONE;`
223			`csr_write <= CSR_WRITE_NONE;`
224			`mem_op <= MEMOP_TYPE_NONE;`
225			`decode_exception <= '0';`
226			`count_instruction_out <= '0';`
227			`elsif stall = '0' then`
228			`pc <= pc_in;`
229			`count_instruction_out <= count_instruction_in;`
230
231			`-- Register signals:`
232			`rd_write_out <= rd_write_in;`
233			`rd_addr_out <= rd_addr_in;`
234			`rs1_addr <= rs1_addr_in;`
235			`rs2_addr <= rs2_addr_in;`
236
237			`-- ALU signals:`
238			`alu_op <= alu_op_in;`
239			`alu_x_src <= alu_x_src_in;`
240			`alu_y_src <= alu_y_src_in;`
241
242			`-- Control signals:`
243			`branch <= branch_in;`
244			`mem_op <= mem_op_in;`
245			`mem_size <= mem_size_in;`
246
247			`-- Constant values:`
248			`immediate <= immediate_in;`
249			`shamt <= shamt_in;`
250			`funct3 <= funct3_in;`
251
252			`-- CSR signals:`
253			`csr_write <= csr_write_in;`
254			`csr_addr <= csr_addr_in;`
255			`csr_use_immediate <= csr_use_immediate_in;`
256			`csr_writeable <= csr_writeable_in;`
257
258			`-- Exception vector base:`
259	58	skordal	`mtvec <= mtvec_in;`
260			`mie <= mie_in;`
261	2	skordal
262			`-- Instruction decoder exceptions:`
263			`decode_exception <= decode_exception_in;`
264			`decode_exception_cause <= decode_exception_cause_in;`
265			`end if;`
266			`end if;`
267			`end process pipeline_register;`
268
269			`set_data_size: process(mem_size)`
270			`begin`
271			`case mem_size is`
272			`when MEMOP_SIZE_BYTE =>`
273			`dmem_data_size <= b"01";`
274			`when MEMOP_SIZE_HALFWORD =>`
275			`dmem_data_size <= b"10";`
276			`when MEMOP_SIZE_WORD =>`
277			`dmem_data_size <= b"00";`
278			`when others =>`
279			`dmem_data_size <= b"11";`
280			`end case;`
281			`end process set_data_size;`
282
283	58	skordal	`get_irq_num: process(irq, exception_context_forwarded, mie_forwarded)`
284	2	skordal	`variable temp : std_logic_vector(3 downto 0);`
285			`begin`
286			`temp := (others => '0');`
287
288			`for i in 0 to 7 loop`
289	58	skordal	`if irq(i) = '1' and mie_forwarded(24 + i) = '1' then`
290	2	skordal	`temp := std_logic_vector(to_unsigned(i, temp'length));`
291			`exit;`
292			`end if;`
293			`end loop;`
294
295			`irq_asserted_num <= temp;`
296			`end process get_irq_num;`
297
298			`data_misalign_check: process(mem_size, alu_result)`
299			`begin`
300			`case mem_size is`
301			`when MEMOP_SIZE_HALFWORD =>`
302			`if alu_result(0) /= '0' then`
303			`data_misaligned <= '1';`
304			`else`
305			`data_misaligned <= '0';`
306			`end if;`
307			`when MEMOP_SIZE_WORD =>`
308			`if alu_result(1 downto 0) /= b"00" then`
309			`data_misaligned <= '1';`
310			`else`
311			`data_misaligned <= '0';`
312			`end if;`
313			`when others =>`
314			`data_misaligned <= '0';`
315			`end case;`
316			`end process data_misalign_check;`
317
318	18	skordal	`instr_misalign_check: process(jump_target, branch, branch_condition, do_jump)`
319	17	skordal	`begin`
320			`if jump_target(1 downto 0) /= b"00" and do_jump = '1' then`
321			`instr_misaligned <= '1';`
322			`else`
323			`instr_misaligned <= '0';`
324			`end if;`
325			`end process instr_misalign_check;`
326	2	skordal
327			`find_exception_cause: process(decode_exception, decode_exception_cause, mem_op,`
328	58	skordal	`data_misaligned, instr_misaligned, irq_asserted, irq_asserted_num, mie_forwarded,`
329			`software_interrupt, timer_interrupt, exception_context_forwarded)`
330	2	skordal	`begin`
331			`if irq_asserted = '1' then`
332			`exception_cause <= std_logic_vector(unsigned(CSR_CAUSE_IRQ_BASE) + unsigned(irq_asserted_num));`
333	58	skordal	`elsif software_interrupt = '1' and mie_forwarded(CSR_MIE_MSIE) = '1' and exception_context_forwarded.ie = '1' then`
334			`exception_cause <= CSR_CAUSE_SOFTWARE_INT;`
335			`elsif timer_interrupt = '1' and mie_forwarded(CSR_MIE_MTIE) = '1' and exception_context_forwarded.ie = '1' then`
336			`exception_cause <= CSR_CAUSE_TIMER_INT;`
337	2	skordal	`elsif decode_exception = '1' then`
338			`exception_cause <= decode_exception_cause;`
339			`elsif mem_op = MEMOP_TYPE_INVALID then`
340			`exception_cause <= CSR_CAUSE_INVALID_INSTR;`
341			`elsif instr_misaligned = '1' then`
342			`exception_cause <= CSR_CAUSE_INSTR_MISALIGN;`
343			`elsif data_misaligned = '1' and mem_op = MEMOP_TYPE_STORE then`
344			`exception_cause <= CSR_CAUSE_STORE_MISALIGN;`
345			`elsif data_misaligned = '1' and memop_is_load(mem_op) then`
346			`exception_cause <= CSR_CAUSE_LOAD_MISALIGN;`
347			`else`
348			`exception_cause <= CSR_CAUSE_NONE;`
349			`end if;`
350			`end process find_exception_cause;`
351
352	58	skordal	`find_exception_addr: process(instr_misaligned, data_misaligned, jump_target, alu_result)`
353	2	skordal	`begin`
354			`if instr_misaligned = '1' then`
355	58	skordal	`exception_addr <= jump_target;`
356	2	skordal	`elsif data_misaligned = '1' then`
357	58	skordal	`exception_addr <= alu_result;`
358	2	skordal	`else`
359	58	skordal	`exception_addr <= (others => '0');`
360	2	skordal	`end if;`
361	58	skordal	`end process find_exception_addr;`
362	2	skordal
363			`calc_jump_tgt: process(branch, pc, rs1_forwarded, immediate, csr_value_forwarded)`
364			`begin`
365			`case branch is`
366			`when BRANCH_JUMP \| BRANCH_CONDITIONAL =>`
367			`jump_target <= std_logic_vector(unsigned(pc) + unsigned(immediate));`
368			`when BRANCH_JUMP_INDIRECT =>`
369			`jump_target <= std_logic_vector(unsigned(rs1_forwarded) + unsigned(immediate));`
370			`when BRANCH_SRET =>`
371	58	skordal	`jump_target <= csr_value_forwarded;`
372	2	skordal	`when others =>`
373			`jump_target <= (others => '0');`
374			`end case;`
375			`end process calc_jump_tgt;`
376
377			`alu_x_mux: entity work.pp_alu_mux`
378			`port map(`
379			`source => alu_x_src,`
380			`register_value => rs1_forwarded,`
381			`immediate_value => immediate,`
382			`shamt_value => shamt,`
383			`pc_value => pc,`
384			`csr_value => csr_value_forwarded,`
385			`output => alu_x`
386			`);`
387
388			`alu_y_mux: entity work.pp_alu_mux`
389			`port map(`
390			`source => alu_y_src,`
391			`register_value => rs2_forwarded,`
392			`immediate_value => immediate,`
393			`shamt_value => shamt,`
394			`pc_value => pc,`
395			`csr_value => csr_value_forwarded,`
396			`output => alu_y`
397			`);`
398
399			`alu_x_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs1_addr,`
400			`rs1_data, wb_rd_write, wb_rd_addr, wb_rd_value)`
401			`begin`
402			`if mem_rd_write = '1' and mem_rd_addr = rs1_addr and mem_rd_addr /= b"00000" then`
403			`rs1_forwarded <= mem_rd_value;`
404			`elsif wb_rd_write = '1' and wb_rd_addr = rs1_addr and wb_rd_addr /= b"00000" then`
405			`rs1_forwarded <= wb_rd_value;`
406			`else`
407			`rs1_forwarded <= rs1_data;`
408			`end if;`
409			`end process alu_x_forward;`
410
411			`alu_y_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs2_addr,`
412			`rs2_data, wb_rd_write, wb_rd_addr, wb_rd_value)`
413			`begin`
414			`if mem_rd_write = '1' and mem_rd_addr = rs2_addr and mem_rd_addr /= b"00000" then`
415			`rs2_forwarded <= mem_rd_value;`
416			`elsif wb_rd_write = '1' and wb_rd_addr = rs2_addr and wb_rd_addr /= b"00000" then`
417			`rs2_forwarded <= wb_rd_value;`
418			`else`
419			`rs2_forwarded <= rs2_data;`
420			`end if;`
421			`end process alu_y_forward;`
422
423			`csr_forward: process(mem_csr_write, wb_csr_write, csr_addr, mem_csr_addr, wb_csr_addr,`
424			`csr_value, mem_csr_value, wb_csr_value, csr_writeable, mem_exception, wb_exception,`
425			`mem_exception_context, wb_exception_context)`
426			`begin`
427	58	skordal	`if csr_addr = CSR_MCAUSE and mem_exception = '1' then`
428	2	skordal	`csr_value_forwarded <= to_std_logic_vector(mem_exception_context.cause);`
429	58	skordal	`elsif csr_addr = CSR_MSTATUS and mem_exception = '1' then`
430			`csr_value_forwarded <= csr_make_mstatus(mem_exception_context.ie, mem_exception_context.ie1);`
431			`elsif csr_addr = CSR_MBADADDR and mem_exception = '1' then`
432			`csr_value_forwarded <= mem_exception_context.badaddr;`
433	2	skordal	`elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = csr_addr and csr_writeable then`
434			`csr_value_forwarded <= mem_csr_value;`
435	58	skordal	`elsif csr_addr = CSR_MCAUSE and wb_exception = '1' then`
436	2	skordal	`csr_value_forwarded <= to_std_logic_vector(wb_exception_context.cause);`
437	58	skordal	`elsif csr_addr = CSR_MSTATUS and wb_exception = '1' then`
438			`csr_value_forwarded <= csr_make_mstatus(wb_exception_context.ie, wb_exception_context.ie1);`
439			`elsif csr_addr = CSR_MBADADDR and wb_exception = '1' then`
440			`csr_value_forwarded <= wb_exception_context.badaddr;`
441	2	skordal	`elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = csr_addr and csr_writeable then`
442			`csr_value_forwarded <= wb_csr_value;`
443			`else`
444			`csr_value_forwarded <= csr_value;`
445			`end if;`
446			`end process csr_forward;`
447
448	58	skordal	`mtvec_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,`
449			`wb_csr_write, wb_csr_addr, wb_csr_value, mtvec)`
450	2	skordal	`begin`
451	58	skordal	`if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MTVEC then`
452			`mtvec_forwarded <= mem_csr_value;`
453			`elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MTVEC then`
454			`mtvec_forwarded <= wb_csr_value;`
455	2	skordal	`else`
456	58	skordal	`mtvec_forwarded <= mtvec;`
457	2	skordal	`end if;`
458	58	skordal	`end process mtvec_forward;`
459	2	skordal
460	58	skordal	`mie_forward: process(mem_csr_write, mem_csr_addr, mem_csr_value,`
461			`wb_csr_write, wb_csr_addr, wb_csr_value, mie)`
462			`begin`
463			`if mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MIE then`
464			`mie_forwarded <= mem_csr_value;`
465			`elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MIE then`
466			`mie_forwarded <= wb_csr_value;`
467			`else`
468			`mie_forwarded <= mie;`
469			`end if;`
470			`end process mie_forward;`
471
472	2	skordal	`exception_ctx_forward: process(mem_exception, wb_exception, mem_exception_context, wb_exception_context,`
473	58	skordal	`exception_cause, exception_addr, mem_csr_write, mem_csr_addr, mem_csr_value,`
474			`wb_csr_write, wb_csr_addr, wb_csr_value, ie_in, ie1_in)`
475	2	skordal	`begin`
476			`if mem_exception = '1' then`
477			`exception_context_forwarded <= mem_exception_context;`
478	58	skordal	`elsif mem_csr_write /= CSR_WRITE_NONE and mem_csr_addr = CSR_MSTATUS then`
479	2	skordal	`exception_context_forwarded <= (`
480	58	skordal	`ie => mem_csr_value(CSR_SR_IE),`
481			`ie1 => mem_csr_value(CSR_SR_IE1),`
482			`cause => exception_cause,`
483			`badaddr => exception_addr);`
484	2	skordal	`elsif wb_exception = '1' then`
485			`exception_context_forwarded <= wb_exception_context;`
486	58	skordal	`elsif wb_csr_write /= CSR_WRITE_NONE and wb_csr_addr = CSR_MSTATUS then`
487	2	skordal	`exception_context_forwarded <= (`
488	58	skordal	`ie => wb_csr_value(CSR_SR_IE),`
489			`ie1 => wb_csr_value(CSR_SR_IE1),`
490			`cause => exception_cause,`
491			`badaddr => exception_addr);`
492	2	skordal	`else`
493	58	skordal	`exception_context_forwarded.ie <= ie_in;`
494			`exception_context_forwarded.ie1 <= ie1_in;`
495	2	skordal	`exception_context_forwarded.cause <= exception_cause;`
496	58	skordal	`exception_context_forwarded.badaddr <= exception_addr;`
497	2	skordal	`end if;`
498			`end process exception_ctx_forward;`
499
500			`detect_load_hazard: process(mem_mem_op, mem_rd_addr, rs1_addr, rs2_addr,`

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[/] [potato/] [trunk/] [src/] [pp_execute.vhd] - Blame information for rev 58