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[/] [potato/] [trunk/] [src/] [pp_fifo.vhd] - Blame information for rev 30

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-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
 
--! @brief A generic FIFO module.
--! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.
entity pp_fifo is
        generic(
                DEPTH : natural := 64;
                WIDTH : natural := 31
        );
        port(
                -- Control lines:
                clk   : in std_logic;
                reset : in std_logic;
 
                -- Status lines:
                full  : out std_logic;
                empty : out std_logic;
 
                -- Data in:
                data_in   : in  std_logic_vector(WIDTH - 1 downto 0);
                data_out  : out std_logic_vector(WIDTH - 1 downto 0);
                push, pop : in std_logic
        );
end entity pp_fifo;
 
architecture behaviour of pp_fifo is
 
        type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
        shared variable memory : memory_array := (others => (others => '0'));
 
        subtype index_type is integer range 0 to DEPTH - 1;
        signal top, bottom : index_type;
 
        type fifo_op is (FIFO_POP, FIFO_PUSH);
        signal prev_op : fifo_op := FIFO_POP;
 
begin
 
        empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';
        full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';
 
        read: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                bottom <= 0;
                        else
                                if pop = '1' then
                                        data_out <= memory(bottom);
                                        bottom <= (bottom + 1) mod DEPTH;
                                end if;
                        end if;
                end if;
        end process read;
 
        write: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                top <= 0;
                        else
                                if push = '1' then
                                        memory(top) := data_in;
                                        top <= (top + 1) mod DEPTH;
                                end if;
                        end if;
                end if;
        end process write;
 
        set_prev_op: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                prev_op <= FIFO_POP;
                        else
                                if push = '1' and pop = '1' then
                                        prev_op <= FIFO_POP;
                                elsif push = '1' then
                                        prev_op <= FIFO_PUSH;
                                elsif pop = '1' then
                                        prev_op <= FIFO_POP;
                                end if;
                        end if;
                end if;
        end process set_prev_op;
 
end architecture behaviour;

Line No.	Rev	Author	Line
1	10	skordal	`-- The Potato Processor - A simple processor for FPGAs`
2			`-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>`
3	11	skordal	`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4	10	skordal
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7
8			`--! @brief A generic FIFO module.`
9			`--! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.`
10			`entity pp_fifo is`
11			`generic(`
12			`DEPTH : natural := 64;`
13			`WIDTH : natural := 31`
14			`);`
15			`port(`
16			`-- Control lines:`
17			`clk : in std_logic;`
18			`reset : in std_logic;`
19
20			`-- Status lines:`
21			`full : out std_logic;`
22			`empty : out std_logic;`
23
24			`-- Data in:`
25			`data_in : in std_logic_vector(WIDTH - 1 downto 0);`
26			`data_out : out std_logic_vector(WIDTH - 1 downto 0);`
27			`push, pop : in std_logic`
28			`);`
29			`end entity pp_fifo;`
30
31			`architecture behaviour of pp_fifo is`
32
33			`type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);`
34			`shared variable memory : memory_array := (others => (others => '0'));`
35
36			`subtype index_type is integer range 0 to DEPTH - 1;`
37			`signal top, bottom : index_type;`
38
39			`type fifo_op is (FIFO_POP, FIFO_PUSH);`
40			`signal prev_op : fifo_op := FIFO_POP;`
41
42			`begin`
43
44			`empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';`
45			`full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';`
46
47			`read: process(clk)`
48			`begin`
49			`if rising_edge(clk) then`
50			`if reset = '1' then`
51			`bottom <= 0;`
52			`else`
53			`if pop = '1' then`
54			`data_out <= memory(bottom);`
55			`bottom <= (bottom + 1) mod DEPTH;`
56			`end if;`
57			`end if;`
58			`end if;`
59			`end process read;`
60
61			`write: process(clk)`
62			`begin`
63			`if rising_edge(clk) then`
64			`if reset = '1' then`
65			`top <= 0;`
66			`else`
67			`if push = '1' then`
68			`memory(top) := data_in;`
69			`top <= (top + 1) mod DEPTH;`
70			`end if;`
71			`end if;`
72			`end if;`
73			`end process write;`
74
75			`set_prev_op: process(clk)`
76			`begin`
77			`if rising_edge(clk) then`
78			`if reset = '1' then`
79			`prev_op <= FIFO_POP;`
80			`else`
81			`if push = '1' and pop = '1' then`
82			`prev_op <= FIFO_POP;`
83			`elsif push = '1' then`
84			`prev_op <= FIFO_PUSH;`
85			`elsif pop = '1' then`
86			`prev_op <= FIFO_POP;`
87			`end if;`
88			`end if;`
89			`end if;`
90			`end process set_prev_op;`
91
92			`end architecture behaviour;`

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[/] [potato/] [trunk/] [src/] [pp_fifo.vhd] - Blame information for rev 30