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[/] [potato/] [trunk/] [src/] [pp_icache.vhd] - Blame information for rev 63

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1 25 skordal
-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.pp_types.all;
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use work.pp_utilities.all;
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12 44 skordal
--! @brief Simple read-only direct-mapped instruction cache.
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entity pp_icache is
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        generic(
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                LINE_SIZE : natural := 4;  --! Number of words per cache line
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                NUM_LINES : natural := 128 --! Number of lines in the cache
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        );
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        port(
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                clk   : in std_logic;
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                reset : in std_logic;
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                -- Control interface:
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                cache_enable    : in std_logic;
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                cache_flush     : in std_logic;
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                cached_areas    : in std_logic_vector(31 downto 0);
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                -- Memory interface:
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                mem_address_in   : in  std_logic_vector(31 downto 0);
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                mem_data_in      : in  std_logic_vector(31 downto 0);
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                mem_data_out     : out std_logic_vector(31 downto 0);
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                mem_data_size    : in  std_logic_vector( 1 downto 0);
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                mem_read_req     : in  std_logic;
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                mem_read_ack     : out std_logic;
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                mem_write_req    : in  std_logic;
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                mem_write_ack    : out std_logic;
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                -- Wishbone interface:
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                wb_inputs  : in wishbone_master_inputs;
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                wb_outputs : out wishbone_master_outputs
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        );
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end entity pp_icache;
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43 44 skordal
architecture behaviour of pp_icache is
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45 44 skordal
        -- Counter types:
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        subtype line_counter_type is natural range 0 to NUM_LINES;
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        subtype word_counter_type is natural range 0 to LINE_SIZE;
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49 44 skordal
        -- Cache line types:
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        subtype cache_line_type is std_logic_vector((LINE_SIZE * 32) - 1 downto 0);
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        type cache_line_word_array is array(0 to LINE_SIZE - 1) of std_logic_vector(31 downto 0);
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        type cache_line_array is array(0 to NUM_LINES - 1) of cache_line_type;
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        -- Cache tag type:
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        subtype cache_tag_type is std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0);
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        type cache_tag_array is array(0 to NUM_LINES - 1) of cache_tag_type;
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        -- Cache memories:
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        signal cache_memory : cache_line_array;
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        signal tag_memory   : cache_tag_array;
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        signal valid        : std_logic_vector(NUM_LINES - 1 downto 0) := (others => '0');
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        attribute ram_style : string;
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        attribute ram_style of cache_memory: signal is "block";
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        --attribute ram_style of tag_memory: signal is "block";
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        -- Cache controller signals:
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        type state_type is (IDLE, CACHE_READ_STALL, SINGLE_READ, SINGLE_WRITE,
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                LOAD_CACHELINE_START, LOAD_CACHELINE_WAIT_ACK, LOAD_CACHELINE_FINISH);
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        signal state : state_type := IDLE;
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72 44 skordal
        -- Is the current input address in the cache?
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        signal input_address_cached : boolean;
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        -- Input address components:
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        signal input_address_line : std_logic_vector(log2(NUM_LINES) - 1 downto 0);
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        signal input_address_word : std_logic_vector(log2(LINE_SIZE) - 1 downto 0);
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        signal input_address_tag  : std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0);
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        -- Cacheline matching the current input address:
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        signal current_cache_line, cache_lookup : cache_line_type;
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        signal current_cache_line_words : cache_line_word_array;
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        signal current_tag : cache_tag_type;
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        -- Base address to store a cacheline to:
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        signal cl_store_address : std_logic_vector(31 downto log2(LINE_SIZE * 4));
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        -- Base address to load a cacheline from:
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        signal cl_load_address  : std_logic_vector(31 downto log2(LINE_SIZE * 4));
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        -- Cache line to load:
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        signal cl_current_line : line_counter_type;
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        -- Current word being loaded/stored:
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        signal cl_current_word  : word_counter_type;
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        -- Buffer for holding a cache line while loading:
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        signal load_buffer : cache_line_type;
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        signal load_buffer_tag : cache_tag_type;
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        -- Causes a cache line to be stored in the cache memory:
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        signal store_cache_line : std_logic;
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101
        -- Set when the current input address matches a cache line:
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        signal cache_hit : std_logic;
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104
        -- For regular reads:
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        signal read_ack : std_logic;
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        signal read_data_out : std_logic_vector(31 downto 0);
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108
        -- For regular writes:
109
        signal write_ack : std_logic;
110
 
111 25 skordal
        -- Gets the amount to shift output data to the processor with for requests of size != 32 bits:
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        function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
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                return natural is
114
        begin
115
                case size is
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                        when b"01" =>
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                                case address(1 downto 0) is
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                                        when b"00" =>
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                                                return 0;
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                                        when b"01" =>
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                                                return 8;
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                                        when b"10" =>
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                                                return 16;
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                                        when b"11" =>
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                                                return 24;
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                                        when others =>
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                                                return 0;
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                                end case;
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                        when b"10" =>
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                                if address(1) = '0' then
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                                        return 0;
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                                else
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                                        return 16;
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                                end if;
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                        when others =>
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                                return 0;
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                end case;
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        end function get_data_shift;
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140
begin
141
 
142 44 skordal
        --assert is_pow2(LINE_SIZE) report "Cache line size must be a power of 2!" severity FAILURE;
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        --assert is_pow2(NUM_LINES) report "Number of cache lines must be a power of 2!" severity FAILURE;
144 25 skordal
 
145
        -- Check if the current input address should be/is in the cache:
146 44 skordal
        input_address_cached <= cached_areas(to_integer(unsigned(mem_address_in(31 downto 27)))) = '1';
147 25 skordal
 
148 44 skordal
        mem_data_out <= current_cache_line_words(to_integer(unsigned(input_address_word))) when
149
                        input_address_cached and cache_enable = '1' and cache_flush = '0'
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                else read_data_out;
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        mem_read_ack <= (cache_hit and mem_read_req)
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                when state = IDLE and input_address_cached and cache_enable = '1' and cache_flush = '0'
153
                else read_ack;
154
        write_ack <= wb_inputs.ack when state = SINGLE_WRITE else '0';
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        mem_write_ack <= write_ack;
156 25 skordal
 
157 44 skordal
        input_address_line <= mem_address_in(log2(LINE_SIZE * 4) + log2(NUM_LINES) - 1 downto log2(LINE_SIZE * 4));
158
        input_address_tag  <= mem_address_in(31 downto log2(LINE_SIZE * 4) + log2(NUM_LINES));
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160
        find_word: process(clk)
161
        begin
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                if rising_edge(clk) then
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                        input_address_word <= mem_address_in(log2(LINE_SIZE * 4) - 1 downto 2);
164
                end if;
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        end process find_word;
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167
        cacheline_lookup: process(clk)
168
        begin
169
                if rising_edge(clk) then
170
                        if store_cache_line = '1' then
171
                                cache_memory(cl_current_line) <= load_buffer;
172
                        end if;
173
 
174
                        current_cache_line <= cache_memory(to_integer(unsigned(input_address_line)));
175
                end if;
176
        end process cacheline_lookup;
177
 
178
        decompose_cache_line: for i in 0 to LINE_SIZE - 1 generate
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                current_cache_line_words(i) <= current_cache_line(32 * i + 31 downto 32 * i);
180
        end generate decompose_cache_line;
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182
        tag_lookup: process(clk)
183
        begin
184
                if rising_edge(clk) then
185
                        if reset = '1' then
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                                cache_hit <= '0';
187
                        else
188
                                if store_cache_line = '1' then
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                                        tag_memory(cl_current_line) <= load_buffer_tag;
190
                                end if;
191
 
192
                                current_tag <= tag_memory(to_integer(unsigned(input_address_line)));
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                                cache_hit <= valid(to_integer(unsigned(input_address_line))) and to_std_logic(tag_memory(to_integer(unsigned(input_address_line))) = input_address_tag);
194
                        end if;
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                end if;
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        end process tag_lookup;
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198 25 skordal
        controller: process(clk)
199 44 skordal
                variable current_word : std_logic_vector(31 downto 0);
200 25 skordal
        begin
201
                if rising_edge(clk) then
202
                        if reset = '1' then
203
                                state <= IDLE;
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                                wb_outputs.cyc <= '0';
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                                wb_outputs.stb <= '0';
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                                store_cache_line <= '0';
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                                read_ack <= '0';
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                                valid <= (others => '0');
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                                read_data_out <= (others => '0');
210 25 skordal
                        else
211
                                case state is
212
                                        when IDLE =>
213 44 skordal
                                                read_ack <= '0';
214
                                                if cache_flush = '1' then
215
                                                        valid <= (others => '0');
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                                                elsif input_address_cached and cache_enable = '1' then
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                                                        if (mem_read_req = '1' or mem_write_req = '1') and cache_hit = '0' then
218
                                                                wb_outputs.adr <= mem_address_in(31 downto log2(LINE_SIZE * 4)) & (log2(LINE_SIZE * 4) - 1 downto 0 => '0');
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                                                                wb_outputs.cyc <= '1';
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                                                                wb_outputs.we <= '0';
221
                                                                wb_outputs.sel <= (others => '1');
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                                                                load_buffer_tag <= input_address_tag;
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                                                                cl_load_address <= mem_address_in(31 downto log2(LINE_SIZE * 4));
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                                                                cl_store_address <= input_address_tag & input_address_line;
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                                                                cl_current_line <= to_integer(unsigned(input_address_line));
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                                                                cl_current_word <= 0;
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                                                                state <= LOAD_CACHELINE_START;
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                                                        end if;
229
                                                else
230
                                                        if mem_read_req = '1' and read_ack = '0' then            -- Do an uncached read
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                                                                wb_outputs.adr <= mem_address_in;
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                                                                wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address_in);
233 25 skordal
                                                                wb_outputs.cyc <= '1';
234
                                                                wb_outputs.stb <= '1';
235
                                                                wb_outputs.we <= '0';
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                                                                state <= SINGLE_READ;
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                                                        elsif mem_write_req = '1' then  -- Do an uncached write
238
                                                                wb_outputs.adr <= mem_address_in;
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                                                                wb_outputs.dat <= std_logic_vector(shift_left(unsigned(mem_data_in),
240
                                                                        get_data_shift(mem_data_size, mem_address_in)));
241 44 skordal
                                                                wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address_in);
242 25 skordal
                                                                wb_outputs.cyc <= '1';
243
                                                                wb_outputs.stb <= '1';
244
                                                                wb_outputs.we <= '1';
245
                                                                state <= SINGLE_WRITE;
246
                                                        end if;
247 44 skordal
                                                end if;
248
                                        when CACHE_READ_STALL =>
249
                                                state <= IDLE;
250 25 skordal
                                        when SINGLE_READ =>
251
                                                if wb_inputs.ack = '1' then
252 44 skordal
                                                        read_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
253 25 skordal
                                                                get_data_shift(mem_data_size, mem_address_in)));
254
                                                        wb_outputs.cyc <= '0';
255
                                                        wb_outputs.stb <= '0';
256 44 skordal
                                                        read_ack <= '1';
257 25 skordal
                                                        state <= IDLE;
258
                                                end if;
259
                                        when SINGLE_WRITE =>
260
                                                if wb_inputs.ack = '1' then
261
                                                        wb_outputs.cyc <= '0';
262
                                                        wb_outputs.stb <= '0';
263
                                                        wb_outputs.we <= '0';
264
                                                        state <= IDLE;
265
                                                end if;
266 44 skordal
                                        when LOAD_CACHELINE_START =>
267
                                                wb_outputs.stb <= '1';
268
                                                wb_outputs.we <= '0';
269
                                                wb_outputs.adr <= cl_load_address & std_logic_vector(to_unsigned(cl_current_word, log2(LINE_SIZE))) & b"00";
270
                                                state <= LOAD_CACHELINE_WAIT_ACK;
271
                                        when LOAD_CACHELINE_WAIT_ACK =>
272
                                                if wb_inputs.ack = '1' then
273
                                                        wb_outputs.stb <= '0';
274
                                                        load_buffer(cl_current_word * 32 + 31 downto cl_current_word * 32) <= wb_inputs.dat;
275
                                                        if natural(cl_current_word) = LINE_SIZE - 1 then
276
                                                                wb_outputs.cyc <= '0';
277
                                                                store_cache_line <= '1';
278
                                                                state <= LOAD_CACHELINE_FINISH;
279
                                                        else
280
                                                                cl_current_word <= cl_current_word + 1;
281
                                                                state <= LOAD_CACHELINE_START;
282
                                                        end if;
283
                                                end if;
284
                                        when LOAD_CACHELINE_FINISH =>
285
                                                store_cache_line <= '0';
286
                                                valid(cl_current_line) <= '1';
287
                                                state <= CACHE_READ_STALL;
288 25 skordal
                                end case;
289
                        end if;
290
                end if;
291
        end process controller;
292
 
293
end architecture behaviour;

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