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[/] [potato/] [trunk/] [src/] [pp_wb_arbiter.vhd] - Blame information for rev 54

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-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.pp_types.all;
 
--! @brief Simple priority-based wishbone arbiter.
--! This module is used as an arbiter between the instruction and data caches.
entity pp_wb_arbiter is
        port(
                clk   : in std_logic;
                reset : in std_logic;
 
                -- Wishbone input 1:
                m1_inputs  : out wishbone_master_inputs;
                m1_outputs : in  wishbone_master_outputs;
 
                -- Wishbone input 2:
                m2_inputs  : out wishbone_master_inputs;
                m2_outputs : in  wishbone_master_outputs;
 
                -- Wishbone interface:
                wb_adr_out : out std_logic_vector(31 downto 0);
                wb_sel_out : out std_logic_vector( 3 downto 0);
                wb_cyc_out : out std_logic;
                wb_stb_out : out std_logic;
                wb_we_out  : out std_logic;
                wb_dat_out : out std_logic_vector(31 downto 0);
                wb_dat_in  : in  std_logic_vector(31 downto 0);
                wb_ack_in  : in  std_logic
        );
end entity pp_wb_arbiter;
 
architecture behaviour of pp_wb_arbiter is
 
        type state_type is (IDLE, M1_BUSY, M2_BUSY);
        signal state : state_type := IDLE;
 
begin
 
        m1_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M1_BUSY else (ack => '0', dat => (others => '0'));
        m2_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M2_BUSY else (ack => '0', dat => (others => '0'));
 
        output_mux: process(state, m1_outputs, m2_outputs)
        begin
                case state is
                        when IDLE =>
                                wb_adr_out <= (others => '0');
                                wb_sel_out <= (others => '0');
                                wb_dat_out <= (others => '0');
                                wb_cyc_out <= '0';
                                wb_stb_out <= '0';
                                wb_we_out <= '0';
                        when M1_BUSY =>
                                wb_adr_out <= m1_outputs.adr;
                                wb_sel_out <= m1_outputs.sel;
                                wb_dat_out <= m1_outputs.dat;
                                wb_cyc_out <= m1_outputs.cyc;
                                wb_stb_out <= m1_outputs.stb;
                                wb_we_out <= m1_outputs.we;
                        when M2_BUSY =>
                                wb_adr_out <= m2_outputs.adr;
                                wb_sel_out <= m2_outputs.sel;
                                wb_dat_out <= m2_outputs.dat;
                                wb_cyc_out <= m2_outputs.cyc;
                                wb_stb_out <= m2_outputs.stb;
                                wb_we_out <= m2_outputs.we;
                end case;
        end process output_mux;
 
        controller: process(clk)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                state <= IDLE;
                        else
                                case state is
                                        when IDLE =>
                                                if m1_outputs.cyc = '1' then
                                                        state <= M1_BUSY;
                                                elsif m2_outputs.cyc = '1' then
                                                        state <= M2_BUSY;
                                                end if;
                                        when M1_BUSY =>
                                                if m1_outputs.cyc = '0' then
                                                        state <= IDLE;
                                                end if;
                                        when M2_BUSY =>
                                                if m2_outputs.cyc = '0' then
                                                        state <= IDLE;
                                                end if;
                                end case;
                        end if;
                end if;
        end process controller;
 
end architecture behaviour;

Line No.	Rev	Author	Line
1	25	skordal	`-- The Potato Processor - A simple processor for FPGAs`
2			`-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>`
3			`-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>`
4
5			`library ieee;`
6			`use ieee.std_logic_1164.all;`
7
8			`use work.pp_types.all;`
9
10			`--! @brief Simple priority-based wishbone arbiter.`
11			`--! This module is used as an arbiter between the instruction and data caches.`
12			`entity pp_wb_arbiter is`
13			`port(`
14			`clk : in std_logic;`
15			`reset : in std_logic;`
16
17			`-- Wishbone input 1:`
18			`m1_inputs : out wishbone_master_inputs;`
19			`m1_outputs : in wishbone_master_outputs;`
20
21			`-- Wishbone input 2:`
22			`m2_inputs : out wishbone_master_inputs;`
23			`m2_outputs : in wishbone_master_outputs;`
24
25			`-- Wishbone interface:`
26			`wb_adr_out : out std_logic_vector(31 downto 0);`
27			`wb_sel_out : out std_logic_vector( 3 downto 0);`
28			`wb_cyc_out : out std_logic;`
29			`wb_stb_out : out std_logic;`
30			`wb_we_out : out std_logic;`
31			`wb_dat_out : out std_logic_vector(31 downto 0);`
32			`wb_dat_in : in std_logic_vector(31 downto 0);`
33			`wb_ack_in : in std_logic`
34			`);`
35			`end entity pp_wb_arbiter;`
36
37			`architecture behaviour of pp_wb_arbiter is`
38
39			`type state_type is (IDLE, M1_BUSY, M2_BUSY);`
40			`signal state : state_type := IDLE;`
41
42			`begin`
43
44			`m1_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M1_BUSY else (ack => '0', dat => (others => '0'));`
45			`m2_inputs <= (ack => wb_ack_in, dat => wb_dat_in) when state = M2_BUSY else (ack => '0', dat => (others => '0'));`
46
47			`output_mux: process(state, m1_outputs, m2_outputs)`
48			`begin`
49			`case state is`
50			`when IDLE =>`
51			`wb_adr_out <= (others => '0');`
52			`wb_sel_out <= (others => '0');`
53			`wb_dat_out <= (others => '0');`
54			`wb_cyc_out <= '0';`
55			`wb_stb_out <= '0';`
56			`wb_we_out <= '0';`
57			`when M1_BUSY =>`
58			`wb_adr_out <= m1_outputs.adr;`
59			`wb_sel_out <= m1_outputs.sel;`
60			`wb_dat_out <= m1_outputs.dat;`
61			`wb_cyc_out <= m1_outputs.cyc;`
62			`wb_stb_out <= m1_outputs.stb;`
63			`wb_we_out <= m1_outputs.we;`
64			`when M2_BUSY =>`
65			`wb_adr_out <= m2_outputs.adr;`
66			`wb_sel_out <= m2_outputs.sel;`
67			`wb_dat_out <= m2_outputs.dat;`
68			`wb_cyc_out <= m2_outputs.cyc;`
69			`wb_stb_out <= m2_outputs.stb;`
70			`wb_we_out <= m2_outputs.we;`
71			`end case;`
72			`end process output_mux;`
73
74			`controller: process(clk)`
75			`begin`
76			`if rising_edge(clk) then`
77			`if reset = '1' then`
78	29	skordal	`state <= IDLE;`
79	25	skordal	`else`
80			`case state is`
81			`when IDLE =>`
82			`if m1_outputs.cyc = '1' then`
83			`state <= M1_BUSY;`
84			`elsif m2_outputs.cyc = '1' then`
85			`state <= M2_BUSY;`
86			`end if;`
87			`when M1_BUSY =>`
88			`if m1_outputs.cyc = '0' then`
89			`state <= IDLE;`
90			`end if;`
91			`when M2_BUSY =>`
92			`if m2_outputs.cyc = '0' then`
93			`state <= IDLE;`
94			`end if;`
95			`end case;`
96			`end if;`
97			`end if;`
98			`end process controller;`
99
100			`end architecture behaviour;`

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[/] [potato/] [trunk/] [src/] [pp_wb_arbiter.vhd] - Blame information for rev 54