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-- VHDL Test Bench Created from source file powerseq_mod.vhd -- 12:53:48 10/07/2024

--

-- Notes: 

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 

-- that these types always be used for the top-level I/O of a design in order 

-- to guarantee that the testbench will bind correctly to the post-implementation 

-- simulation model.

--

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY testbench IS

END testbench;

ARCHITECTURE behavior OF testbench IS

        COMPONENT powerseq_mod

        PORT(

                clk : IN std_logic;

                reset_n : IN std_logic;

                forcepoweron : IN std_logic;

                PSEQ_RAIL_PG : IN std_logic_vector(127 downto 0);

                thermal_n : IN std_logic;

                all_on : IN std_logic;

                PSEQ_RAIL_EN : OUT std_logic_vector(127 downto 0);

                failed_rails : OUT std_logic_vector(255 downto 0);

                pfailure : OUT std_logic;

                tick_out : OUT std_logic;

                pseqstate_out : OUT std_logic_vector(3 downto 0);

                all_pgood : OUT std_logic

                );

        END COMPONENT;

  constant clk_per         : time    :=  40 ns; -- 25 MHz clk

        signal clk : std_logic := '0';

        SIGNAL reset_n :  std_logic;

        SIGNAL forcepoweron :  std_logic;

        SIGNAL PSEQ_RAIL_EN :  std_logic_vector(127 downto 0);

        SIGNAL PSEQ_RAIL_PG :  std_logic_vector(127 downto 0);

        SIGNAL thermal_n :  std_logic;

        SIGNAL failed_rails :  std_logic_vector(255 downto 0);

        SIGNAL pfailure :  std_logic;

        SIGNAL tick_out :  std_logic;

        SIGNAL pseqstate_out :  std_logic_vector(3 downto 0);

        SIGNAL all_on :  std_logic;

        SIGNAL all_pgood :  std_logic;

BEGIN

        uut: powerseq_mod PORT MAP(

                clk => clk,

                reset_n => reset_n,

                forcepoweron => forcepoweron,

                PSEQ_RAIL_EN => PSEQ_RAIL_EN,

                PSEQ_RAIL_PG => PSEQ_RAIL_PG,

                thermal_n => thermal_n,

                failed_rails => failed_rails,

                pfailure => pfailure,

                tick_out => tick_out,

                pseqstate_out => pseqstate_out,

                all_on => all_on,

                all_pgood => all_pgood

        );

-- *** Test Bench - User Defined Section ***

  ckp: process begin

    clk <= not clk; wait for (clk_per/2);

  end process;

   tb : PROCESS

   BEGIN

    -- signal assertion sequence, manual edit

reset_n   <= '0';

forcepoweron <= '0';

thermal_n <= '1';

PSEQ_RAIL_PG(5 downto 0) <= (others => '0');

PSEQ_RAIL_PG(127 downto 6) <= (others => '1');

all_on <= '0';

wait for (50*clk_per);

reset_n    <= '1';

wait for (50*clk_per);

all_on <= '1';

wait for (50*clk_per);

PSEQ_RAIL_PG(0) <= '1';

wait for (50*clk_per);

PSEQ_RAIL_PG(1) <= '1';

wait for (50*clk_per);

PSEQ_RAIL_PG(2) <= '1';

wait for (50*clk_per);

PSEQ_RAIL_PG(3) <= '1';

wait for (50*clk_per);

PSEQ_RAIL_PG(4) <= '1';

wait for (50*clk_per);

PSEQ_RAIL_PG(5) <= '1';

wait for (50*clk_per);

--# ordered seq down:

wait for (100us);

all_on <= '0';

wait for (100 us);

all_on <= '1';

--# thermal fault and recovery:

--wait for (100us);

--thermal_n <= '0';

--wait for (50*clk_per);

--thermal_n <= '1';

--wait for (50*clk_per);

--all_on <= '0';

--wait for (50*clk_per);

--all_on <= '1';

--# rail fault in S0 and recovery:

--wait for (100us);

--PSEQ_RAIL_PG(5) <= '0';

--wait for (50*clk_per);

--PSEQ_RAIL_PG(5) <= '1';

--wait for (50*clk_per);

--all_on <= '0';

--wait for (50*clk_per);

--all_on <= '1';

      wait; -- will wait forever

   END PROCESS;

-- *** End Test Bench - User Defined Section ***

END;