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[/] [ppx16/] [trunk/] [bench/] [vhdl/] [TestBench84.vhd] - Blame information for rev 23

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1 3 jesus
library IEEE;
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use IEEE.std_logic_1164.all;
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entity TestBench84 is
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end TestBench84;
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architecture behaviour of TestBench84 is
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        signal Clk              : std_logic := '0';
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        signal Reset_n  : std_logic := '0';
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        signal T0CKI    : std_logic := '0';
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        signal INT              : std_logic := '0';
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        signal Port_A   : std_logic_vector(7 downto 0);
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        signal Port_B   : std_logic_vector(7 downto 0);
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begin
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        p1 : entity work.P16F84 port map (Clk, Reset_n, T0CKI, INT, Port_A, Port_B);
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        Clk <= not Clk after 50 ns;
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        Reset_n <= '1' after 200 ns;
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        INT <= not INT after 20 us;
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end;

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