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--
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-- PIC16xx compatible microcontroller core
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--
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-- Version : 0222
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t51/
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--
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-- Limitations :
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--
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-- File history :
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity PPX_ALU is
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generic(
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InstructionLength : integer;
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TriState : boolean := false
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);
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port (
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Clk : in std_logic;
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ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
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A : in std_logic_vector(7 downto 0);
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B : in std_logic_vector(7 downto 0);
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Q : out std_logic_vector(7 downto 0);
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Skip : in std_logic;
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Carry : in std_logic;
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Z_Skip : out std_logic;
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STATUS_d : out std_logic_vector(2 downto 0);
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STATUS_Wr : out std_logic_vector(2 downto 0)
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);
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end PPX_ALU;
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architecture rtl of PPX_ALU is
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procedure AddSub(A : std_logic_vector(3 downto 0);
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B : std_logic_vector(3 downto 0);
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Sub : std_logic;
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Carry_In : std_logic;
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signal Res : out std_logic_vector(3 downto 0);
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signal Carry : out std_logic) is
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variable B_i : unsigned(4 downto 0);
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variable Full_Carry : unsigned(4 downto 0);
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variable Res_i : unsigned(4 downto 0);
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begin
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if Sub = '1' then
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B_i := "0" & not unsigned(B);
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else
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B_i := "0" & unsigned(B);
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end if;
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if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
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Full_Carry := "00001";
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else
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Full_Carry := "00000";
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end if;
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Res_i := unsigned("0" & A) + B_i + Full_Carry;
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Carry <= Res_i(4);
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Res <= std_logic_vector(Res_i(3 downto 0));
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end;
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signal Do_IDTEST : std_logic;
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signal Do_ADD : std_logic;
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signal Do_SUB : std_logic;
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signal Do_DEC : std_logic;
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signal Do_INC : std_logic;
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signal Do_AND : std_logic;
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signal Do_OR : std_logic;
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signal Do_XOR : std_logic;
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signal Do_COM : std_logic;
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signal Do_RRF : std_logic;
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signal Do_RLF : std_logic;
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signal Do_SWAP : std_logic;
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signal Do_BITCLR : std_logic;
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signal Do_BITSET : std_logic;
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signal Do_BITTESTCLR : std_logic;
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signal Do_BITTESTSET : std_logic;
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signal Do_CLR : std_logic;
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signal Inst_Top : std_logic_vector(11 downto 0);
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signal Bit_Pattern : std_logic_vector(7 downto 0);
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signal Bit_Test : std_logic_vector(7 downto 0);
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signal Q_ID : std_logic_vector(7 downto 0);
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signal Q_L : std_logic_vector(7 downto 0);
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signal Q_C : std_logic_vector(7 downto 0);
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signal Q_RR : std_logic_vector(7 downto 0);
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signal Q_RL : std_logic_vector(7 downto 0);
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signal Q_S : std_logic_vector(7 downto 0);
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signal Q_BC : std_logic_vector(7 downto 0);
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signal Q_BS : std_logic_vector(7 downto 0);
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signal DC_i : std_logic;
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signal AddSubRes : std_logic_vector(8 downto 0);
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signal Q_i : std_logic_vector(7 downto 0);
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begin
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Q <= Q_i;
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Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
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gNoTri : if not TriState generate
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Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else
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AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else
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Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
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Q_C when Do_COM = '1' else
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Q_RR when Do_RRF = '1' else
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Q_RL when Do_RLF = '1' else
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Q_S when Do_SWAP = '1' else
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Q_BC when Do_BITCLR = '1' else
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Q_BS when Do_BITSET = '1' else
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"00000000";
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end generate;
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gTri : if TriState generate
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Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
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Q_i <= AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else "ZZZZZZZZ";
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Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
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Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
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Q_i <= Q_RR when Do_RRF = '1' else "ZZZZZZZZ";
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Q_i <= Q_RL when Do_RLF = '1' else "ZZZZZZZZ";
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Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
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Q_i <= Q_BC when Do_BITCLR = '1' else "ZZZZZZZZ";
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Q_i <= Q_BS when Do_BITSET = '1' else "ZZZZZZZZ";
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Q_i <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
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end generate;
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process (Clk)
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begin
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if Clk'event and Clk = '1' then
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Do_ADD <= '0';
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Do_SUB <= '0';
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Do_AND <= '0';
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Do_OR <= '0';
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Do_XOR <= '0';
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Do_IDTEST <= '0';
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Do_INC <= '0';
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Do_DEC <= '0';
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Do_COM <= '0';
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Do_RRF <= '0';
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Do_RLF <= '0';
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Do_SWAP <= '0';
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Do_BITCLR <= '0';
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Do_BITSET <= '0';
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Do_BITTESTCLR <= '0';
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Do_BITTESTSET <= '0';
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Do_CLR <= '0';
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if Skip = '0' then
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if InstructionLength = 12 then
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if Inst_Top(11 downto 6) = "000111" then
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-- ADDWF
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Do_ADD <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000010" then
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-- SUBWF
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Do_SUB <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 8) = "1110" then
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-- ANDWF, ANDLW
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Do_AND <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 8) = "1101" then
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-- IORWF, IORLW
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Do_OR <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 8) = "1111" then
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-- XORWF, XORLW
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Do_XOR <= '1';
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end if;
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else
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if Inst_Top(11 downto 6) = "000111" or Inst_Top(11 downto 7) = "11111" then
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-- ADDWF, ADDLW
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Do_ADD <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000010" or Inst_Top(11 downto 7) = "11110" then
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-- SUBWF, SUBLW
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Do_SUB <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 6) = "111001" then
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-- ANDWF, ANDLW
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Do_AND <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 6) = "111000" then
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-- IORWF, IORLW
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Do_OR <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 6) = "111010" then
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-- XORWF, XORLW
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Do_XOR <= '1';
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end if;
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end if;
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if Inst_Top(11 downto 9) = "001" and Inst_Top(7 downto 6) = "11" then
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-- INC/DEC w conditional skip
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Do_IDTEST <= '1';
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end if;
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if Inst_Top(11 downto 6) = "001010" or Inst_Top(11 downto 6) = "001111" then
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-- INCF, INCFSZ
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Do_INC <= '1';
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end if;
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if Inst_Top(11 downto 6) = "000011" or Inst_Top(11 downto 6) = "001011" then
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-- DECF, DECFSZ,
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Do_DEC <= '1';
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end if;
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if Inst_Top(11 downto 6) = "001001" then
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-- COMF
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Do_COM <= '1';
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end if;
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if Inst_Top(11 downto 6) = "001100" then
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-- RRF
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Do_RRF <= '1';
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end if;
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if Inst_Top(11 downto 6) = "001101" then
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-- RLF
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Do_RLF <= '1';
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end if;
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if Inst_Top(11 downto 6) = "001110" then
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-- SWAPF
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Do_SWAP <= '1';
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end if;
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if Inst_Top(11 downto 8) = "0100" then
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-- BCF
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Do_BITCLR <= '1';
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end if;
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if Inst_Top(11 downto 8) = "0101" then
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-- BSF
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Do_BITSET <= '1';
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end if;
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if Inst_Top(11 downto 8) = "0110" then
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-- BTFSC
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Do_BITTESTCLR <= '1';
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end if;
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if Inst_Top(11 downto 8) = "0111" then
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-- BTFSS
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274 |
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Do_BITTESTSET <= '1';
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end if;
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276 |
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if Inst_Top(11 downto 6) = "000001" then
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277 |
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-- CLRF, CLRW
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Do_CLR <= '1';
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end if;
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280 |
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end if;
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281 |
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282 |
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case Inst_Top(7 downto 5) is
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283 |
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when "000" =>
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284 |
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Bit_Pattern <= "00000001";
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285 |
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when "001" =>
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286 |
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Bit_Pattern <= "00000010";
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287 |
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when "010" =>
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288 |
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Bit_Pattern <= "00000100";
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289 |
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when "011" =>
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290 |
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Bit_Pattern <= "00001000";
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291 |
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when "100" =>
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292 |
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Bit_Pattern <= "00010000";
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293 |
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when "101" =>
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294 |
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Bit_Pattern <= "00100000";
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295 |
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when "110" =>
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296 |
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Bit_Pattern <= "01000000";
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297 |
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when others =>
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298 |
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Bit_Pattern <= "10000000";
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299 |
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end case;
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300 |
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end if;
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301 |
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end process;
|
302 |
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303 |
11 |
jesus |
Q_ID <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
|
304 |
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std_logic_vector(unsigned(A) - 1);
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305 |
3 |
jesus |
|
306 |
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AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
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307 |
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AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
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308 |
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309 |
11 |
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Q_L <= (A and B) when Do_AND = '1' else
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310 |
3 |
jesus |
(A or B) when Do_OR = '1' else
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311 |
11 |
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(A xor B);
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312 |
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Q_C <= (not A);
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313 |
3 |
jesus |
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314 |
11 |
jesus |
Q_RR <= Carry & A(7 downto 1);
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315 |
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Q_RL <= A(6 downto 0) & Carry;
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316 |
3 |
jesus |
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317 |
11 |
jesus |
Q_S <= A(3 downto 0) & A(7 downto 4);
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318 |
3 |
jesus |
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319 |
11 |
jesus |
Q_BC <= ((not Bit_Pattern) and A);
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320 |
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Q_BS <= (Bit_Pattern or A);
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321 |
3 |
jesus |
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322 |
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Bit_Test <= Bit_Pattern and A;
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323 |
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324 |
11 |
jesus |
Z_Skip <= '1' when (Do_IDTEST = '1' and Q_ID = "00000000") or
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325 |
3 |
jesus |
(Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
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326 |
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(Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
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327 |
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328 |
11 |
jesus |
STATUS_d(2) <= '1' when Q_i(7 downto 0) = "00000000" else '0';
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329 |
3 |
jesus |
STATUS_d(1) <= DC_i;
|
330 |
|
|
STATUS_d(0) <= A(0) when Do_RRF = '1' else
|
331 |
|
|
A(7) when Do_RLF = '1' else
|
332 |
|
|
AddSubRes(8);
|
333 |
|
|
|
334 |
|
|
-- Z
|
335 |
|
|
STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
|
336 |
|
|
((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
|
337 |
|
|
Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
|
338 |
11 |
jesus |
Do_CLR = '1' or Do_COM = '1' else '0';
|
339 |
3 |
jesus |
-- DC
|
340 |
|
|
STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
|
341 |
|
|
-- C
|
342 |
|
|
STATUS_Wr(0) <= '1' when Do_SUB = '1' or Do_ADD = '1' or Do_RRF = '1' or Do_RLF = '1' else '0';
|
343 |
|
|
|
344 |
|
|
end;
|