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jesus |
--
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-- PIC16xx compatible microcontroller core
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--
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-- Version : 0146
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t51/
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--
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-- Limitations :
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-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
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-- other registers must be implemented externally including GPR
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--
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-- File history :
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity PPX_Port is
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port(
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Clk : in std_logic;
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Reset_n : in std_logic;
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Port_CS : in std_logic;
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Rd : in std_logic;
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Wr : in std_logic;
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Tris_Rd : in std_logic;
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Tris_Wr : in std_logic;
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Data_In : in std_logic_vector(7 downto 0);
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Data_Out : out std_logic_vector(7 downto 0);
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IOPort : inout std_logic_vector(7 downto 0)
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);
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end PPX_Port;
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architecture rtl of PPX_Port is
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signal Tris : std_logic_vector(7 downto 0);
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signal Port_Output : std_logic_vector(7 downto 0);
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signal Port_Input : std_logic_vector(7 downto 0);
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begin
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IOPort(0) <= Port_Output(0) when Tris(0) = '0' else 'Z';
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IOPort(1) <= Port_Output(1) when Tris(1) = '0' else 'Z';
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IOPort(2) <= Port_Output(2) when Tris(2) = '0' else 'Z';
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IOPort(3) <= Port_Output(3) when Tris(3) = '0' else 'Z';
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IOPort(4) <= Port_Output(4) when Tris(4) = '0' else 'Z';
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IOPort(5) <= Port_Output(5) when Tris(5) = '0' else 'Z';
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IOPort(6) <= Port_Output(6) when Tris(6) = '0' else 'Z';
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IOPort(7) <= Port_Output(7) when Tris(7) = '0' else 'Z';
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Data_Out <= Port_Input when Port_CS = '1' and Rd = '1' else "ZZZZZZZZ";
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process (Clk)
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begin
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if Clk'event and Clk = '1' then
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Port_Input <= IOPort; -- Synchronise input
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if Port_CS = '1' and Wr = '1' then
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Port_Output <= Data_In;
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Port_Input <= Data_In;
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end if;
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end if;
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end process;
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Data_Out <= Tris when Tris_Rd = '1' else "ZZZZZZZZ";
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process (Reset_n, Clk)
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begin
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if Reset_n = '0' then
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Tris <= "11111111";
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elsif Clk'event and Clk = '1' then
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if Tris_Wr = '1' then
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Tris <= Data_In;
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end if;
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end if;
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end process;
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end;
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