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\documentclass{gajewski}
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\bibliographystyle{IEEEtran}
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%%%%%%%%%%%%%%%%%
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% Document variables
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%%%%%%%%%%%%%%%%%
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\docDate{ \today }
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\docID{Present cipher (32 bit input)}
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\docRevision{0.2}
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\docStatus{Draft}
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\docTitle{\mbox{Present Cipher (32 bit input)}}
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\authorName{\mbox{Krzysztof Gajewski} \\ and opencores.org}
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\authorURL{www.opencores.org}
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\authorAddress{\mbox{}}
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\authorEmail{gajos@opencores.org}
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\revisionList{
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0.1 & all & 2014/09/05 & First draft & K. Gajewski \\
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0.2 & all & 2014/09/16 & Some small corrections with the text, typos, etc. & K. Gajewski \\
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}
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\begin{document}
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\maketitle
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\newpage
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\revisionTable
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\newpage
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\tableofcontents
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\newpage
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\section{Introduction}
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Present is \textgravedbl ultra-lightweight\textacutedbl \space block cipher developed by A. Bogdanov et al. and proposed in 2007 \cite{PRESENT}. It uses 64 bit data block and 80 bit or 128 bit key.
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This cipher consists of 32 rounds, during which:
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\begin{itemize}
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\item round key is added to plaintext
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\item plaintext goes through sBoxes (substitution boxes)
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\item plaintext after sBoxes goes through pLayer (permutation layer)
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\item round key is updated
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\end{itemize}
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After that, ciphertext feeds out the output. Briefly algorithm was shown in Fig. \ref{pAlgorithm}.
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.66\textwidth]{img/presentAlgorithm.png}
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\caption{%
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Briefly block scheme of the PRESENT block cipher
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}%
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\label{pAlgorithm}
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\end{center}
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\end{figure}
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In this project Present block cipher works with 80 bit key. Target was Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E \cite{Spartan} on Spartan 3E Starter Board \cite{Digilent} made by Digilent\textsuperscript{\textregistered}. In comparison with "plain" Present cipher project, this core was modified to take 32 bit word at input (plus control word). Output is also 32 bit.
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\textbf{NOTE:}
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This is rather "historical" project and is not recommended for future use.
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\newpage
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\section{Interface}
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Top level component of the Present component with 32 bit input was shown in Fig. \ref{penc}. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. Type for all signals is \texttt{STD\_LOGIC} or \texttt{STD\_LOGIC\_VECTOR}.
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.5\textwidth]{img/PresentEnc.png}
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\caption{%
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Top level of the Present component with 32 bit input
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}%
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\label{penc}
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\end{center}
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\end{figure}
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\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
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\hline \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\
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\hline \texttt{input} & 32 & in & input data - both key and plaintext. \\
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\hline \texttt{ctrl} & 4 & in & control bus for sending commands to the core. \\
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\hline \texttt{clk} & 1 & in & clock signal for the component\\
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\hline \texttt{reset} & 1 & in & \emph{asynchronous} reset signal. \\
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\hline \texttt{output} & 32 & out & output data - ciphertext. \\
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\hline \texttt{ready} & 1 & out & signal informing about end of encoding process. \newline "0" - wait until end of data encoding. \newline "1" - end of the encoding process, output data available. \\
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\hline
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\end{tabularx}
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\captionof{table}{Input/Output signals of the Present component with 32 bit input}
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\newpage
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\section{State machine workflow}
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Overall internal structure of the Present component with 32 bit input is similar to the structure shown in \cite{PRESENT}. To conform 64 bit plaintext, 80 bit key and 32 bit output data, multiplexer-like blocks was added to fit data. Additionally, control logic was added in the state machine. It was shown in Fig. \ref{presentSM}.
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.5\textwidth]{img/SM.jpg}
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\caption{%
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State machine of the Present component
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}%
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\label{presentSM}
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\end{center}
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\end{figure}
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State machine consist of nine states \texttt{NOP}, \texttt{RDK1}, \texttt{RDK2}, \texttt{RDK3}, \texttt{RDT1}, \texttt{RDT2}, \texttt{COD}, \texttt{CTO1}, \texttt{CTO2}. \texttt{NOP} is the default state after resetting the core. This state is active as long as control bus (\texttt{ctrl}) don't have \texttt{crdk1} command at the input.
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\texttt{RDKx} states are responsible for reading the key from the input. They are changing when suitable command appears at the \texttt{ctrl} input (\ref{presentSM}). When another commands appear, the state is changing to the \texttt{NOP} state. When command are left constant, given state is not changing.
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\texttt{RDTx} states are responsible for reading the plaintext from the input. They are changing when suitable command appears at the \texttt{ctrl} input (\ref{presentSM}). When another commands appear, the state is changing to \texttt{NOP} state. When command are left constant, given state is not changing.
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During the \texttt{COD} state encoding process start. If encoding process ends (after 32 clock cycles, \texttt{info = "00"} signal from the counter), state machine automaticly goes to the \texttt{CTO1} state. When commands another than \texttt{ccod} appear, the state is changing to the \texttt{NOP} state. When command are left constant encoding process is working.
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\texttt{CTOx} states are responsible for sending the ciphertext to the output. They are changing when suitable command appears at the \texttt{ctrl} input (\ref{presentSM}). When another commands appear, the state is changing to the \texttt{NOP} state. When command are left constant, given state is not changing.
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\newpage
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\section{FPGA implementations}
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The component has only been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. Appropriate setup files was prepared with the use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./32BitIO/syn/XC3ES500/} directory. Implementation in FPGA device \textbf{was not done} in this project (due to rather historical issues and nonconventional build of these core). Makefile was tested in Windows 8 with the use of Cygwin for 64-bit Windows.
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Synthesis results was given in Fig. \ref{SynResults}
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\begin{tabularx}{\textwidth}{|p{45mm}|p{30mm}|p{30mm}|X|}
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\hline \multicolumn{4}{|c|}{Xilinx \textregistered Spartan 3E XC3S500E FPGA in FG320 package} \\
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\hline \bf{Parameter} & \bf{Used} & \bf{Available} & \bf{Utilization}\\
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\hline Number of Slices & 313 & 4656 & 6\% \\
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\hline Number of Slice Flip Flops & 262 & 9312 & 2\% \\
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\hline Number of 4 input LUTs & 460 & 9312 & 4\% \\
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\hline Number of bonded IOBs & 71 & 232 & 30\% \\
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\hline Number of GCLKs & 1 & 24 & 4\%\\
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\hline Minimum period & 4.250 ns & - & - \\
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\hline Maximum Frequency & 235 MHz & - & - \\
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\hline
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\end{tabularx}
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\label{SynResults}
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\captionof{table}{Synthesis results for Spartan 3E XC3S500E}
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Possible change in used FPGA device may be possible in steps given below\footnotemark[1]:
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\begin{enumerate}
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\item Copy \texttt{./32BitIO/syn/XC3ES500/} directory to another one like \texttt{./32BitIO/syn/YOUR\_FPGA\_SYMBOL/}
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\item Go to \texttt{./32BitIO/syn/YOUR\_FPGA\_SYMBOL/} directory.
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\item In \texttt{PresentEnc.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_CODE}
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\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_CODE}
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\end{enumerate}
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\footnotetext[1]{This solution was not tested and is based on my own observations.}
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\newpage
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\section{Simulation}
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Self-checking test bench were provided to the components used for Present encoder. In case of whole Present with 32 bit input encoder this test bench was not self-checking. This is due to historical character of this project. They are stored in \texttt{./32BitIO/bench/vhdl} directory. Suitable configuration files and Makefile used for running test bench was stored in
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\texttt{./32BitIO/sim/rtl\_sim/bin} directory. Appropriate test vectors was taken from \cite{PRESENT}.
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Makefile was prepared to make "manual run" of tests. If You want to perform it without gui, remove \texttt{-gui} option in Makefaile.
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\newpage
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\section{Troubleshooting}
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During work with Windows 8 64-bit and and Xilinx\textsuperscript{\textregistered} ISE 64-bit some problems may occur:
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\begin{enumerate}
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\item Xilinx may be unable to open projects in Project Navigator.
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\item When you run \texttt{make} in Cygwin and perform testbench it would be unable to open ISIM gui.
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\item When you run ISIM gui (*.exe test bench file) it hangs out or anti virus protection opens.
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\end{enumerate}
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To solve problems listed above you have to perform steps listed below:
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\begin{enumerate}
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\item You have to rename libraries \texttt{libPortabilityNOSH.dll} to \texttt{libPortability.dll} from \texttt{nt64} directories (\href{http://www.gadgetfactory.net/2013/09/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/}{http://www.gadgetfactory.net/2013/09/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/})
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\item Firstly, install Cygwin X11 (\href{http://stackoverflow.com/questions/9393462/cannot-launch-git-gui-using-cygwin-on-windows}{http://stackoverflow.com/questions/9393462/cannot-launch-git-gui-using-cygwin-on-windows})
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\item Temporary switch off anti virus protection.
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\end{enumerate}
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\newpage
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\section{License and Liability}
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Copyright \textcopyright 2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and-or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from \href{http://www.opencores.org/lgpl.shtml}{http://www.opencores.org/lgpl.shtml}
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Xilinx, Spartan3E is registered trademark of Xilinx Inc. 2100 Logic Drive, San Jose CA USA
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\newpage
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\bibliography{bibliography}
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\end{document}
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