| 1 |
4 |
gajos |
-----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- Present - a lightweight block cipher project ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the Present - a lightweight block ----
|
| 6 |
|
|
---- cipher project ----
|
| 7 |
|
|
---- http://www.http://opencores.org/project,present ----
|
| 8 |
|
|
---- ----
|
| 9 |
|
|
---- Description: ----
|
| 10 |
|
|
---- This file contains types and constant used by this ----
|
| 11 |
|
|
---- implementation of Present project ----
|
| 12 |
|
|
---- To Do: ----
|
| 13 |
|
|
---- ----
|
| 14 |
|
|
---- Author(s): ----
|
| 15 |
|
|
---- - Krzysztof Gajewski, gajos@opencores.org ----
|
| 16 |
|
|
---- k.gajewski@gmail.com ----
|
| 17 |
|
|
---- ----
|
| 18 |
|
|
-----------------------------------------------------------------------
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
|
| 21 |
|
|
---- ----
|
| 22 |
|
|
---- This source file may be used and distributed without ----
|
| 23 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 24 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 25 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 26 |
|
|
---- ----
|
| 27 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 28 |
|
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
| 29 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 30 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 31 |
|
|
---- later version. ----
|
| 32 |
|
|
---- ----
|
| 33 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 34 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 35 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 36 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 37 |
|
|
---- details. ----
|
| 38 |
|
|
---- ----
|
| 39 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 40 |
|
|
---- Public License along with this source; if not, download it ----
|
| 41 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 42 |
|
|
---- ----
|
| 43 |
|
|
-----------------------------------------------------------------------
|
| 44 |
2 |
gajos |
-- Package File Template
|
| 45 |
|
|
--
|
| 46 |
|
|
-- Purpose: This package defines supplemental types, subtypes,
|
| 47 |
|
|
-- constants, and functions
|
| 48 |
|
|
|
| 49 |
|
|
|
| 50 |
|
|
library IEEE;
|
| 51 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
| 52 |
|
|
package kody is
|
| 53 |
|
|
-- type for PresentStateMachine to control the datapath & circuit --
|
| 54 |
|
|
type stany is (NOP, RDK1, RDK2, RDK3, RDT1, RDT2, COD, CTO1, CTO2);
|
| 55 |
|
|
-- constant as control command from input --
|
| 56 |
|
|
constant cnop : std_logic_vector(3 downto 0) := "0000"; --0 no operations
|
| 57 |
|
|
constant cdec : std_logic_vector(3 downto 0) := "0001"; --1 decode text
|
| 58 |
|
|
constant crdk1 : std_logic_vector(3 downto 0) := "0010"; --2 read key part 1
|
| 59 |
|
|
constant crdk2 : std_logic_vector(3 downto 0) := "0011"; --3 read key part 2
|
| 60 |
|
|
constant crdk3 : std_logic_vector(3 downto 0) := "0100"; --4 read key part 3
|
| 61 |
|
|
constant cmkd : std_logic_vector(3 downto 0) := "0101"; --5 make decrypt key
|
| 62 |
|
|
constant ccod : std_logic_vector(3 downto 0) := "0110"; --6 code text
|
| 63 |
|
|
constant crdt1 : std_logic_vector(3 downto 0) := "0111"; --7 read text part 1
|
| 64 |
|
|
constant crdt2 : std_logic_vector(3 downto 0) := "1000"; --8 read text part 2
|
| 65 |
|
|
constant ccto1 : std_logic_vector(3 downto 0) := "1001"; --9 ciphertext output part 1 (LSW)
|
| 66 |
|
|
constant ccto2 : std_logic_vector(3 downto 0) := "1010"; --A ciphertext output part 2 (MSW)
|
| 67 |
|
|
-- For input registers (early version, now for mux's) --
|
| 68 |
|
|
constant in_ld_reg_L : std_logic_vector(1 downto 0) := "00"; -- Load low part of the register (64 & 80 bit)
|
| 69 |
|
|
constant in_ld_reg_H : std_logic_vector(1 downto 0) := "01"; -- Load high part of the register (64 & 80 bit)
|
| 70 |
|
|
constant in_ld_reg_HH : std_logic_vector(1 downto 0) := "10"; -- Load highest part of the register (80 bit only)
|
| 71 |
|
|
constant in_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input)
|
| 72 |
|
|
-- For output register --
|
| 73 |
|
|
constant out_ld_reg : std_logic_vector(1 downto 0) := "00"; -- Load the output register
|
| 74 |
|
|
constant out_reg_L : std_logic_vector(1 downto 0) := "01"; -- send low part of the register to the output
|
| 75 |
|
|
constant out_reg_H : std_logic_vector(1 downto 0) := "10"; -- senf high part of the register to the output
|
| 76 |
|
|
constant out_reg_Z : std_logic_vector(1 downto 0) := "11"; -- High impedance on the line (unused - in this design only for block input)
|
| 77 |
|
|
end kody;
|
