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gajos |
-----------------------------------------------------------------------
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---- ----
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---- Present - a lightweight block cipher project ----
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---- ----
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---- This file is part of the Present - a lightweight block ----
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---- cipher project ----
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---- http://www.http://opencores.org/project,present ----
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---- ----
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---- Description: ----
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---- This is not "strict" implementation of multiplexer but ----
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---- contains its functionality. There are two inputs. One - ----
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---- 32 bit input, and one 64 bit input - because of way, in which ----
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---- Present is working. For more information see below ----
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---- To Do: ----
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---- ----
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---- Author(s): ----
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---- - Krzysztof Gajewski, gajos@opencores.org ----
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---- k.gajewski@gmail.com ----
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---- ----
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-----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and-or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-----------------------------------------------------------------------
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gajos |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.kody.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity mux64 is
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generic (
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w_2 : integer := 2;
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w_32 : integer := 32;
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w_64 : integer := 64
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);
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port(
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i0ctrl : in std_logic_vector (w_2-1 downto 0);
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input0 : in std_logic_vector(w_32-1 downto 0);
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input1 : in std_logic_vector(w_64-1 downto 0);
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ctrl, clk, reset : in std_logic;
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output : inout std_logic_vector(w_64-1 downto 0)
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);
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end mux64;
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architecture Behavioral of mux64 is
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begin
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inne : process (clk, reset)
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begin
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if (reset = '1') then
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output <= (others => '0');
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elsif (clk'Event and clk = '1') then
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if ctrl = '0' then
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gajos |
-- load least significant 32 bits of output from input0 (32 bit wide)
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gajos |
if (i0ctrl = in_ld_reg_L ) then
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output <= output(w_64-1 downto 32) & input0;
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gajos |
-- load most significant 32 bits of output from input0 (32 bit wide)
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gajos |
elsif (i0ctrl = in_ld_reg_H) then
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output <= input0 & output(31 downto 0);
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else
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gajos |
-- do nothing
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gajos |
output <= output;
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gajos |
end if;
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-- on output goes data from 64 bit input
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else
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output <= input1;
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end if;
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end if;
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end process inne;
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end Behavioral;
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