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[/] [present/] [trunk/] [Decode/] [rtl/] [vhdl/] [FullDecoderSM.vhd] - Blame information for rev 4

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1 4 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Present - a lightweight block cipher project                  ----
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----                                                               ----
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---- This file is part of the Present - a lightweight block        ----
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---- cipher project                                                ----
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---- http://www.http://opencores.org/project,present               ----
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----                                                               ----
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---- Description:                                                  ----
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----     State machine for Present decoder. It controls entire     ----
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---- environment for decoding. We can feature 2 'steady states'    ----
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---- and 2 'running states'. For more informations see below       ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
45 3 gajos
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.kody.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity FullDecoderSM is
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        port(
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                key_gen_start : out std_logic;
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                key_gen_ready : in std_logic;
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                decode_start  : out std_logic;
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                decode_ready  : in std_logic;
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                full_decoder_start :in std_logic;
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                full_decoder_ready : out std_logic;
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                clk, reset  :in std_logic
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        );
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end FullDecoderSM;
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architecture Behavioral of FullDecoderSM is
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        signal state : decode_states;
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        signal next_state : decode_states;
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begin
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        states : process(state, full_decoder_start, key_gen_ready, decode_ready)
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                begin
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                        case state is
80 4 gajos
                            ---- It is No operation - waiting for proper data in the input ----
81 3 gajos
                                when NOP =>
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                                        key_gen_start <= '0';
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                                        decode_start <= '0';
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                                        full_decoder_ready <= '0';
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                                        if (full_decoder_start = '1') then
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                                                next_state <= KG_START;
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                                        else
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                                                next_state <= NOP;
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                                        end if;
90 4 gajos
                                ---- It is running key generator for decoding
91 3 gajos
                                when KG_START =>
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                                        key_gen_start <= '1';
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                                        decode_start <= '0';
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                                        full_decoder_ready <= '0';
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                                        if (key_gen_ready = '1') then
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                                                next_state <= DEC_START;
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                                        else
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                                                next_state <= KG_START;
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                                        end if;
100 4 gajos
                                ---- enerated key for decoding is ready. Now we are decoding ----
101 3 gajos
                                when DEC_START   =>
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                                        key_gen_start <= '1';
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                                        decode_start <= '1';
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                                        full_decoder_ready <= '0';
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                                        if (decode_ready = '1') then
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                                                next_state <= DEC_READY;
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                                        else
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                                                next_state <= DEC_START;
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                                        end if;
110 4 gajos
                                ---- Decoding was ended. Waiting for user retrieving data ---- 
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                                ---- and give information about new operation ----
112 3 gajos
                                when DEC_READY =>
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                                        key_gen_start <= '1';
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                                        decode_start <= '1';
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                                        full_decoder_ready <= '1';
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                                        if (full_decoder_start = '1') then
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                                                next_state <= DEC_READY;
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                                        else
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                                                next_state <= NOP;
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                                        end if;
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                        end case;
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                end process states;
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        SM : process (clk, reset)
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                        begin
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                                if (reset = '1') then
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                                        state <= NOP;
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                                elsif (clk'Event and clk = '1') then
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                                        state <= next_state;
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                                end if;
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                        end process SM;
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end Behavioral;
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