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[/] [present/] [trunk/] [Decode/] [rtl/] [vhdl/] [PresentEncKeyGen.vhd] - Blame information for rev 4

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-----------------------------------------------------------------------
----                                                               ----
---- Present - a lightweight block cipher project                  ----
----                                                               ----
---- This file is part of the Present - a lightweight block        ----
---- cipher project                                                ----
---- http://www.http://opencores.org/project,present               ----
----                                                               ----
---- Description:                                                  ----
----     Key generator of Present encoder. It is only those part   ----
---- which is needed for key and cipher decoding by Present        ----
---- decoder.                                                      ----
---- To Do:                                                        ----
----                                                               ----
---- Author(s):                                                    ----
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
----                       k.gajewski@gmail.com                    ----
----                                                               ----
-----------------------------------------------------------------------
----                                                               ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
----                                                               ----
---- This source file may be used and distributed without          ----
---- restriction provided that this copyright statement is not     ----
---- removed from the file and that any derivative work contains   ----
---- the original copyright notice and the associated disclaimer.  ----
----                                                               ----
---- This source file is free software; you can redistribute it    ----
---- and-or modify it under the terms of the GNU Lesser General    ----
---- Public License as published by the Free Software Foundation;  ----
---- either version 2.1 of the License, or (at your option) any    ----
---- later version.                                                ----
----                                                               ----
---- This source is distributed in the hope that it will be        ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
---- PURPOSE. See the GNU Lesser General Public License for more   ----
---- details.                                                      ----
----                                                               ----
---- You should have received a copy of the GNU Lesser General     ----
---- Public License along with this source; if not, download it    ----
---- from http://www.opencores.org/lgpl.shtml                      ----
----                                                               ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity PresentEncKeyGen is
        generic (
                        w_2: integer := 2;
                        w_4: integer := 4;
                        w_5: integer := 5;
                        w_80: integer := 80
        );
        port(
                key             : in std_logic_vector(w_80 - 1 downto 0);
                key_end : out std_logic_vector(w_80 - 1 downto 0);
                start, clk, reset : in std_logic;
                ready : out std_logic
        );
end PresentEncKeyGen;
 
architecture Behavioral of PresentEncKeyGen is
 
        component Reg is
                generic(width : integer := w_80);
                port(
                        input  : in  STD_LOGIC_VECTOR(width - 1 downto 0);
                        output : out STD_LOGIC_VECTOR(width - 1 downto 0);
                        enable : in  STD_LOGIC;
                        clk    : in  STD_LOGIC;
                        reset  : in  STD_LOGIC
                );
        end component Reg;
 
        component AsyncMux is
                generic (
                        width : integer := 80
        );
        port (
                input0 : in  STD_LOGIC_VECTOR(width - 1 downto 0);
                input1 : in  STD_LOGIC_VECTOR(width - 1 downto 0);
                ctrl   : in  STD_LOGIC;
                output : out STD_LOGIC_VECTOR(width - 1 downto 0)
        );
        end component AsyncMux;
 
        component PresentStateMachine is
                generic (
                        w_5 : integer := 5
                );
                port (
                        clk, reset, start : in std_logic;
                        ready, cnt_res, ctrl_mux, RegEn: out std_logic;
                        num : in std_logic_vector (w_5-1 downto 0)
                );
        end component;
 
        component keyupd is
                generic(
                        w_5 : integer := 5;
                        w_80: integer := 80
                );
                port(
                        num : in std_logic_vector(w_5-1 downto 0);
                        key : in std_logic_vector(w_80-1 downto 0);
                        keyout : out std_logic_vector(w_80-1 downto 0)
                );
        end component;
 
        component counter is
                generic (
                        w_5 : integer := 5
                );
                port (
                        clk, reset, cnt_res : in std_logic;
                        num : out std_logic_vector (w_5-1 downto 0)
                );
        end component;
 
    -- signals
 
        signal keynum : std_logic_vector (w_5-1 downto 0);
        signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0);
        signal ready_sig, mux_ctrl,  cnt_res, RegEn : std_logic;
 
        begin
 
            -- connections
 
                mux_80: AsyncMux generic map(width => w_80) port map(
                        input0 => key,
                        input1 => kupd,
                        ctrl => mux_ctrl,
                        output => keyToReg
                );
                regKey : Reg generic map(width => w_80) port map(
                        input  => keyToReg,
                        output  => keyfout,
                        enable  => RegEn,
                        clk  => clk,
                        reset  => reset
                );
                mixer: keyupd port map(
                        key => keyfout,
                        num => keynum,
                        keyout => kupd
                );
                SM: PresentStateMachine port map(
                        start => start,
                        reset => reset,
                        ready => ready_sig,
                        cnt_res => cnt_res,
                        ctrl_mux => mux_ctrl,
                        clk => clk,
                        num => keynum,
                        RegEn => RegEn
                );
                count: counter port map(
                        clk => clk,
                        reset => reset,
                        cnt_res => cnt_res,
                        num => keynum
                );
                key_end <= keyfout;
                ready <= ready_sig;
end Behavioral;

Line No.	Rev	Author	Line
1	4	gajos	`-----------------------------------------------------------------------`
2			`---- ----`
3			`---- Present - a lightweight block cipher project ----`
4			`---- ----`
5			`---- This file is part of the Present - a lightweight block ----`
6			`---- cipher project ----`
7			`---- http://www.http://opencores.org/project,present ----`
8			`---- ----`
9			`---- Description: ----`
10			`---- Key generator of Present encoder. It is only those part ----`
11			`---- which is needed for key and cipher decoding by Present ----`
12			`---- decoder. ----`
13			`---- To Do: ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Krzysztof Gajewski, gajos@opencores.org ----`
17			`---- k.gajewski@gmail.com ----`
18			`---- ----`
19			`-----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2013 Authors and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and-or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`-----------------------------------------------------------------------`
45	3	gajos	`library IEEE;`
46			`use IEEE.STD_LOGIC_1164.ALL;`
47			`use IEEE.STD_LOGIC_ARITH.ALL;`
48			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
49			`use IEEE.NUMERIC_STD.ALL;`
50
51			`entity PresentEncKeyGen is`
52			`generic (`
53			`w_2: integer := 2;`
54			`w_4: integer := 4;`
55			`w_5: integer := 5;`
56			`w_80: integer := 80`
57			`);`
58			`port(`
59			`key : in std_logic_vector(w_80 - 1 downto 0);`
60			`key_end : out std_logic_vector(w_80 - 1 downto 0);`
61			`start, clk, reset : in std_logic;`
62			`ready : out std_logic`
63			`);`
64			`end PresentEncKeyGen;`
65
66			`architecture Behavioral of PresentEncKeyGen is`
67
68			`component Reg is`
69			`generic(width : integer := w_80);`
70			`port(`
71			`input : in STD_LOGIC_VECTOR(width - 1 downto 0);`
72			`output : out STD_LOGIC_VECTOR(width - 1 downto 0);`
73			`enable : in STD_LOGIC;`
74			`clk : in STD_LOGIC;`
75			`reset : in STD_LOGIC`
76			`);`
77			`end component Reg;`
78
79			`component AsyncMux is`
80			`generic (`
81			`width : integer := 80`
82			`);`
83			`port (`
84			`input0 : in STD_LOGIC_VECTOR(width - 1 downto 0);`
85			`input1 : in STD_LOGIC_VECTOR(width - 1 downto 0);`
86			`ctrl : in STD_LOGIC;`
87			`output : out STD_LOGIC_VECTOR(width - 1 downto 0)`
88			`);`
89			`end component AsyncMux;`
90
91			`component PresentStateMachine is`
92			`generic (`
93			`w_5 : integer := 5`
94			`);`
95			`port (`
96			`clk, reset, start : in std_logic;`
97			`ready, cnt_res, ctrl_mux, RegEn: out std_logic;`
98			`num : in std_logic_vector (w_5-1 downto 0)`
99			`);`
100			`end component;`
101
102			`component keyupd is`
103			`generic(`
104			`w_5 : integer := 5;`
105			`w_80: integer := 80`
106			`);`
107			`port(`
108			`num : in std_logic_vector(w_5-1 downto 0);`
109			`key : in std_logic_vector(w_80-1 downto 0);`
110			`keyout : out std_logic_vector(w_80-1 downto 0)`
111			`);`
112			`end component;`
113
114			`component counter is`
115			`generic (`
116			`w_5 : integer := 5`
117			`);`
118			`port (`
119			`clk, reset, cnt_res : in std_logic;`
120			`num : out std_logic_vector (w_5-1 downto 0)`
121			`);`
122			`end component;`
123	4	gajos
124			`-- signals`
125	3	gajos
126			`signal keynum : std_logic_vector (w_5-1 downto 0);`
127			`signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0);`
128			`signal ready_sig, mux_ctrl, cnt_res, RegEn : std_logic;`
129
130			`begin`
131	4	gajos
132			`-- connections`
133
134	3	gajos	`mux_80: AsyncMux generic map(width => w_80) port map(`
135			`input0 => key,`
136			`input1 => kupd,`
137			`ctrl => mux_ctrl,`
138			`output => keyToReg`
139			`);`
140			`regKey : Reg generic map(width => w_80) port map(`
141			`input => keyToReg,`
142			`output => keyfout,`
143			`enable => RegEn,`
144			`clk => clk,`
145			`reset => reset`
146			`);`
147			`mixer: keyupd port map(`
148			`key => keyfout,`
149			`num => keynum,`
150			`keyout => kupd`
151			`);`
152			`SM: PresentStateMachine port map(`
153			`start => start,`
154			`reset => reset,`
155			`ready => ready_sig,`
156			`cnt_res => cnt_res,`
157			`ctrl_mux => mux_ctrl,`
158			`clk => clk,`
159			`num => keynum,`
160			`RegEn => RegEn`
161			`);`
162			`count: counter port map(`
163			`clk => clk,`
164			`reset => reset,`
165			`cnt_res => cnt_res,`
166			`num => keynum`
167			`);`
168			`key_end <= keyfout;`
169			`ready <= ready_sig;`
170			`end Behavioral;`

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[/] [present/] [trunk/] [Decode/] [rtl/] [vhdl/] [PresentEncKeyGen.vhd] - Blame information for rev 4