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[/] [present/] [trunk/] [DecodeTesting/] [bench/] [vhdl/] [PresentDecTB.vhd] - Blame information for rev 4

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1 4 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Present - a lightweight block cipher project                  ----
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----                                                               ----
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---- This file is part of the Present - a lightweight block        ----
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---- cipher project                                                ----
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---- http://www.http://opencores.org/project,present               ----
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----                                                               ----
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---- Description:                                                  ----
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----     Present decoder test bench. Test signals were taken from  ----
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---- 'pure' Presnet encoder simulation (it is proper work, because ----
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---- it was good implementation).                                  ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
45 3 gajos
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY PresentDecTB IS
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END PresentDecTB;
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ARCHITECTURE behavior OF PresentDecTB IS
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT PresentDec
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    PORT(
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         plaintext : IN  std_logic_vector(63 downto 0);
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         key : IN  std_logic_vector(79 downto 0);
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         ciphertext : OUT  std_logic_vector(63 downto 0);
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         start : IN  std_logic;
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         clk : IN  std_logic;
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         reset : IN  std_logic;
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         ready : OUT  std_logic
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        );
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    END COMPONENT;
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   --Inputs
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   signal plaintext : std_logic_vector(63 downto 0) := (others => '0');
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   signal key : std_logic_vector(79 downto 0) := (others => '0');
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   signal start : std_logic := '0';
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   signal clk : std_logic := '0';
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   signal reset : std_logic := '0';
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        --Outputs
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   signal ciphertext : std_logic_vector(63 downto 0);
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   signal ready : std_logic;
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   -- Clock period definitions
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   constant clk_period : time := 10 ns;
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: PresentDec PORT MAP (
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          plaintext => plaintext,
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          key => key,
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          ciphertext => ciphertext,
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          start => start,
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          clk => clk,
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          reset => reset,
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          ready => ready
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin
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                reset <= '1';
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      start <= '0';
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                plaintext <= x"5579c1387b228445";
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                key <= x"6dab31744f41d7008759";
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                wait for 100 ns;
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                reset <= '0';
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                plaintext <= x"5579c1387b228445";
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                key <= x"6dab31744f41d7008759";
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                start <= '1';
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      wait for clk_period*40;
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                start <= '0';
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                wait for clk_period;
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                plaintext <= x"e72c46c0f5945049";
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                key <= x"fe7a548fb60eb167c511";
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                start <= '1';
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      wait for clk_period*40;
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                start <= '0';
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                wait for clk_period;
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                plaintext <= x"a112ffc72f68417b";
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                key <= x"6dab31744f41d7008759";
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                start <= '1';
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      wait for clk_period*40;
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                start <= '0';
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                wait for clk_period;
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                plaintext <= x"3333dcd3213210d2";
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                key <= x"fe7a548fb60eb167c511";
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                start <= '1';
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      wait for clk_period*40;
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                start <= '0';
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                wait for clk_period;
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                assert false severity failure;
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   end process;
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END;

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