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\documentclass{gajewski}
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\bibliographystyle{IEEEtran}
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%%%%%%%%%%%%%%%%%
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% Document variables
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%%%%%%%%%%%%%%%%%
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\docDate{ \today }
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\docID{Present Decoder ("Decode Testing") - with communication channel with PC}
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\docRevision{0.2}
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\docStatus{Draft}
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\docTitle{\mbox{Present Decoder ("Decode Testing") -} \mbox{with communication channel with PC}}
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\docTitleShort{Present Decoder ("Decode Testing")...}
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\authorName{\mbox{Krzysztof Gajewski} \\ and opencores.org}
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\authorURL{www.opencores.org}
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\authorAddress{\mbox{}}
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\authorEmail{gajos@opencores.org}
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\revisionList{
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0.1 & all & 2014/05/25 & First draft & K. Gajewski \\
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0.2 & all & 2014/09/16 & Some small corrections with the text, typos, etc. & K. Gajewski \\
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}
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\begin{document}
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\maketitle
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\newpage
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\revisionTable
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\newpage
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\tableofcontents
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\newpage
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\section{Introduction}
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Present is "ultra-lightweight" block cipher developed by A. Bogdanov et al. and proposed in 2007 \cite{PRESENT}. It uses 64 bit data block and 80 bit or 128 bit key.
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This cipher consists of 32 rounds, during which:
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\begin{itemize}
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\item round key is added to plaintext
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\item plaintext goes through sBoxes (substitution boxes)
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\item plaintext after sBoxes goes through pLayer (permutation layer)
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\item round key is updated
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\end{itemize}
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After that, ciphertext feeds out the output. Briefly algorithm was shown in Fig. \ref{pAlgorithm}
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.66\textwidth]{img/presentAlgorithm.png}
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\caption{%
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Briefly block scheme of the PRESENT block cipher
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}%
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\label{pAlgorithm}
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\end{center}
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\end{figure}
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In subprojects \texttt{Pure} and \texttt{PureTesting} Present encoder components was presented. In this project Present decoder was presented. It was attached by shifting registers to RS-232 core developed by Digilent\textsuperscript{\textregistered} to enable communication with PC. Decoding key is firstly generated, basing on the key used for data coding. Next, input data are decoded (taking into account "inverse" direction to the presented in Fig. \ref{pAlgorithm}), and at last feeds the output. This core works with 80 bit key. Target was Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E \cite{Spartan} on Spartan 3E Starter Board \cite{Digilent} made by Digilent\textsuperscript{\textregistered}.
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\newpage
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\section{Interface}
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Top level component of Present Decode Testing was shown in Fig. \ref{pdectest}. The number of inputs and outputs was limited due to RS-232 component in communication interface. All inputs and outputs are synchronous except \texttt{reset} signal and sampled at rising edge of the clock. All signals are \texttt{STD\_LOGIC}.
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.5\textwidth]{img/PresentDecodeTesting.png}
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\caption{%
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Top level component of the Present Decode Testing
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}%
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\label{pdectest}
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\end{center}
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\end{figure}
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\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
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\hline \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\
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\hline \texttt{clk} & 1 & in & clock signal for the component. \\
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\hline \texttt{DATA\_RXD} & 1 & in & input data signal. \\
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\hline \texttt{reset} & 1 & in & \emph{asynchronous} reset signal.\\
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\hline \texttt{DATA\_TXD} & 1 & out & output data signal. \\
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\hline
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\end{tabularx}
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\captionof{table}{Input/Output signals of the Present Decode Testing component}
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\newpage
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\section{Internal structure and state machine workflow}
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Internal datapath between components was shown in Fig. \ref{pdecinside}. All control signals, \texttt{clk} and \texttt{reset} was omitted for clearance. In these schamatic \texttt{keyReg}, \texttt{textReg} and \texttt{outReg} are shift registers enabling conversion of the input/output serial data into parallel data. They are respectively:
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\begin{itemize}
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\item \texttt{keyReg} - shift register for the key used during decoding,
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\item \texttt{textReg} - shift register for the text to be decoded (to be more clearly \texttt{ciphertext}),
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\item \texttt{outReg} - shift register for the output data to be sendend by RS232 (to be more clearly \texttt{plaintext}).
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\end{itemize}
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\texttt{PresentFullDecoder} - is the decoding core. It was described in \texttt{./Decode/doc/present\_decode.pdf} file ("Decode" subproject documentation). \texttt{RS232} is the serial communication core developed by Digilent\textsuperscript{\textregistered} responsible for the communication with PC computer.
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\texttt{PresentDecodeCommSM} is state machine which manage communication with PC and data conversion before and after data decoding in \texttt{PresentFullDecoder} component.
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.95\textwidth]{img/PresentDecodeCommInside.png}
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\caption{%
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Internal structure of the Present Decode Testing core with communication environment.
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}%
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\label{pdecinside}
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\end{center}
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\end{figure}
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State machine states and transition between them was shown in Fig. \ref{presentDecodeCommSM}.
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\begin{figure}[!ht]%
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\begin{center}
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\includegraphics[width=0.95\textwidth]{img/presentDecodeCommSM.png}
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\caption{%
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State machine of the Present Decode Testing decipher with added communication component
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}%
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\label{presentDecodeCommSM}
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\end{center}
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\end{figure}
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In fact it is the same state machine as in \texttt{Present Pure Testing} subproject, but due to its length, will be reminded. State machine consist of following states:
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\begin{itemize}
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\item \texttt{NOP} - this is the initial state of the state machine. It is set up after resetting the system. If any data appear in the RS-232 input (\texttt{RDAsig = '1'}), this state will be changed.
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\item \texttt{READ\_DATA\_TEXT} / \texttt{READ\_DATA\_KEY} - These states inform the RS-232 component that input data was read (by write enable in \texttt{keyReg} register).
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\item \texttt{DECODE\_READ\_TEXT} / \texttt{DECODE\_READ\_KEY}- In these states the number of performed data reading iterations are checked. Because one RS-232 packet was set to 8 bytes - 8 iterations need to be performed for reading full 64 bit text data input (10 iterations for reading full 80 bit key data input).
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\item \texttt{TEMP\_STATE} / \texttt{TEMP2\_STATE} / \texttt{TEMP\_OUT} - Here the counter is prepared for key reading / decoding / next "decoding session".
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\item \texttt{MOVE\_TEXT} / \texttt{MOVE\_KEY} / - Due to serial data in RS-232 component are stored in 8 bit register, they need to be shifted in appropriate place in given shift registers. It is performed by 8 shifts made in 8 clock cycles.
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\item \texttt{NOP\_FOR\_KEY} - Kind of \texttt{NOP} or wait state until 'key' data will arrive.
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\item \texttt{PRESENT\_ENCODE} - In this state Present decoding is performed. This state is active until Present component informs about ending of the decoding process (\texttt{readySig = '1'}). [In this part the naming may be a little bit confusing, but this not interfere the work of the core]
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\item \texttt{WRITE\_OUT} - state responsible for immediate sending decoded data. It is performed as many number as 64 bits of decoded data will be sent by the RS-232 component to the PC (similarly to "\texttt{DECODE...}" states).
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\item \texttt{MOVE\_OUT} - it is similar state to the previous \texttt{MOVE...} states, but here additionally state machine must wait until output data buffer will be prepared for next data which have to be sent.
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\end{itemize}
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No "lost data" checking, and data correction protocol was performed. It was assumed "ideal channel" for communication. Some states could be "merged" into one state but it will involve more expanded control logic.
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\newpage
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\section{FPGA implementations}
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The component has been verified on a Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package and synthesized with Xilinx ISE 14.2. It was also implemented and practically tested on Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. Appropriate setup files was prepared with the use of ISE Project Navigator, but Makefile scripts was also written. Suitable files was stored in \texttt{./DecodeTesting/syn/XC3ES500/} directory.
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Makefile was tested in Windows 8 with use of Cygwin for 64-bit Windows.
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Synthesis results was given in Fig. \ref{SynResults}
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\begin{tabularx}{\textwidth}{|p{45mm}|p{30mm}|p{30mm}|X|}
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\hline \multicolumn{4}{|c|}{Xilinx\textsuperscript{\textregistered} Spartan 3E XC3S500E FPGA in FG320 package} \\
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\hline \bf{Parameter} & \bf{Used} & \bf{Available} & \bf{Utilization}\\
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\hline Number of Slices & 533 & 4656 & 11\% \\
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\hline Number of Slice Flip Flops & 530 & 9312 & 4\% \\
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\hline Number of 4 input LUTs & 582 & 9312 & 5\% \\
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\hline Number of bonded IOBs & 4 & 232 & 1\% \\
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\hline Number of GCLKs & 2 & 24 & 8\%\\
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\hline Minimum period & 6.343ns & - & - \\
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\hline Maximum Frequency & 157 MHz & - & - \\
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\hline
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\end{tabularx}
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\label{SynResults}
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\captionof{table}{Synthesis results for Spartan 3E XC3S500E}
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Possible change in used FPGA device may be possible in steps given below\footnotemark[1]:
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\begin{enumerate}
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\item Copy \texttt{./DecodeTesting/syn/XC3ES500/} directory to another one like \\ \texttt{./DecodeTesting/syn/YOUR\_FPGA\_SYMBOL/}
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\item Go to \texttt{./DecodeTesting/syn/YOUR\_FPGA\_SYMBOL/} directory.
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\item In \texttt{PresentDecodeComm.xst} file modify the line \texttt{-p xc3s500e-5-fg320} to \texttt{-p YOUR\_FPGA\_CODE}
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\item In \texttt{Makefile} file modify the line \texttt{PLATFORM=xc3s500e-fg320-5} to \texttt{PLATFORM=YOUR\_FPGA\_CODE}
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\end{enumerate}
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\textbf{WARNING!!!}
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With this core there exist one issue related to communication process. It was observed, that every \textbf{first} decoding process after resetting the core, returns incorrect data (not observed during testing in ISE environment). Resending data and performing new calculations fix that. So, using this core it is desirable to force performing first "dummy" calculations after every reset.
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\footnotetext[1]{This solution was not tested and is based on my own observations. Additional care should be taken with *.UCF files - this supplied with this project should be appropriate only for Spartan 3E Starter Board made by Digilent\textsuperscript{\textregistered}. You can make this modifications on your own risk}
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\newpage
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\section{Simulation and software}
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\subsection{Simulation}
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Self-checking test bench were provided to the components used for Present encoder with RS-232 communication. They are stored in \texttt{./DecodeTesting/bench/vhdl} directory. Suitable configuration files and Makefile used for running test bench was stored in \\
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\texttt{./DecodeTesting/sim/rtl\_sim/bin} directory. Appropriate test vectors was taken from \cite{PRESENT}. In \texttt{PresentDecodeCommTB.vhd} file with suitable test files stored in \\
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\texttt{./DecodeTesting/sim/rtl\_sim/bin/test} directory simulation of RS-232 communication was prepared. Due to that only this one test bench is not self checking. Observation and testing of the communication in this case will be most comfortable using isim gui.
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Makefile was prepared to make "manual run" of tests. If You want to perform it without gui, remove \texttt{-gui} option in Makefaile.
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\subsection{Software}
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With this project two tool programs written in Java was included:
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\begin{itemize}
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\item \texttt{PresentDataGenerator} (class with the same file name)
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\item "GUI Application" which consist of two classes (Communication.java and Window.java)
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\end{itemize}
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They were brought into Eclipse project, which can be easy imported. It was tested with Eclipse Indigo version.
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First of them is used to prepare data for \texttt{PresentDecodeCommTB}. It can be used by:
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\begin{itemize}
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\item Setting \texttt{drive}, \texttt{data} and \texttt{key} variables with hexadecimal values as it is desired.
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\item Running the compiler and running program.
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\end{itemize}
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On its output it sends set of bits which are sequentially sent to the PresentDecodeComm component during test bench.
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"GUI application" enables communication with PC by use of RS-232 connection. RS-232 communication in Java is delivered by \texttt{rxtx} library. It was partly based on tutorial which can be found at \cite{GUIComm}.
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This program can be used as follow:
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\begin{itemize}
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\item After connecting FPGA board to the RS-232 port click the "Connect" button.
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\item To the "Data" and "Key" write suitable hexadecimal data used for encoding.
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\item Press "Send" button.
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\item Answer should appear in "Log" box in hexadecimal values.
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\end{itemize}
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These programs were not prepared for unusual cases, so entering intended inappropriate values (like non hexadecimal values) are not recommended.
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\newpage
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\section{Troubleshooting}
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During work with Windows 8 64-bit and and Xilinx\textsuperscript{\textregistered} ISE 64-bit some problems may occur:
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\begin{enumerate}
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\item Xilinx may be unable to open projects in Project Navigator.
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\item When you run \texttt{make} in Cygwin and perform testbench it would be unable to open ISIM gui.
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\item When you run ISIM gui (*.exe test bench file) it hangs out or anti virus protection opens.
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\end{enumerate}
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To solve problems listed above you have to perform steps listed below:
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\begin{enumerate}
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\item You have to rename libraries \texttt{libPortabilityNOSH.dll} to \texttt{libPortability.dll} from \texttt{nt64} directories (\href{http://www.gadgetfactory.net/2013/09/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/}{http://www.gadgetfactory.net/2013/09/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/})
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\item Firstly, install Cygwin X11 (\href{http://stackoverflow.com/questions/9393462/cannot-launch-git-gui-using-cygwin-on-windows}{http://stackoverflow.com/questions/9393462/cannot-launch-git-gui-using-cygwin-on-windows})
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\item Temporary switch off anti virus protection.
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\end{enumerate}
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\newpage
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\section{License and Liability}
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Copyright\textcopyright \space 2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and-or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from \href{http://www.opencores.org/lgpl.shtml}{http://www.opencores.org/lgpl.shtml}
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Xilinx, Spartan3E is registered trademark of Xilinx Inc. 2100 Logic Drive, San Jose CA USA
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\newpage
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\bibliography{bibliography}
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\end{document}
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