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------------------------------------------------------------------------
--  RS232RefCom.vhd
------------------------------------------------------------------------
-- Author:  Dan Pederson
--          Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description:         This file defines a UART which tranfers data from 
--                              serial form to parallel form and vice versa.                    
------------------------------------------------------------------------
-- Revision History:
--  07/15/04 (Created) DanP
--       02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
--                                                                                      in the Clock Dividing Processes
------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Rs232RefComp is
    Port (
                TXD     : out std_logic         := '1';
        RXD     : in  std_logic;
        CLK     : in  std_logic;                                                                --Master Clock
                DBIN    : in  std_logic_vector (7 downto 0);     --Data Bus in
                DBOUT : out std_logic_vector (7 downto 0);       --Data Bus out
                RDA     : inout std_logic;                                              --Read Data Available
                TBE     : inout std_logic       := '1';                 --Transfer Bus Empty
                RD              : in  std_logic;                                        --Read Strobe
                WR              : in  std_logic;                                        --Write Strobe
                PE              : out std_logic;                                        --Parity Error Flag
                FE              : out std_logic;                                        --Frame Error Flag
                OE              : out std_logic;                                        --Overwrite Error Flag
                RST             : in  std_logic := '0'); --Master Reset
end Rs232RefComp;
 
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
 
------------------------------------------------------------------------
--  Local Type Declarations
------------------------------------------------------------------------
        --Receive state machine
        type rstate is (
                strIdle,                        --Idle state
                strEightDelay,  --Delays for 8 clock cycles
                strGetData,             --Shifts in the 8 data bits, and checks parity
                strCheckStop            --Sets framing error flag if Stop bit is wrong
        );
 
        type tstate is (
                sttIdle,                        --Idle state
                sttTransfer,    --Move data into shift register
                sttShift                        --Shift out data
                );
 
        type TBEstate is (
                stbeIdle,
                stbeSetTBE,
                stbeWaitLoad,
                stbeWaitWrite
                );
 
 
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
        constant baudDivide : std_logic_vector(7 downto 0) := "00001101";        --Baud Rate dividor, set now for a rate of 9600.
                                                                                                                                                                                                --Found by dividing 50MHz by 9600 and 16.
        signal rdReg    :  std_logic_vector(7 downto 0) := "00000000";                   --Receive holding register
        signal rdSReg   :  std_logic_vector(9 downto 0) := "1111111111";         --Receive shift register
        signal tfReg    :  std_logic_vector(7 downto 0);                                                         --Transfer holding register
        signal tfSReg  :  std_logic_vector(10 downto 0)  := "11111111111";       --Transfer shift register
        signal clkDiv   :  std_logic_vector(8 downto 0)  := "000000000";         --used for rClk
        signal rClkDiv :  std_logic_vector(3 downto 0)   := "0000";                              --used for tClk
        signal ctr      :  std_logic_vector(3 downto 0)  := "0000";                                      --used for delay times
        signal tfCtr    :  std_logic_vector(3 downto 0)  := "0000";                              --used to delay in transfer
        signal rClk     :  std_logic := '0';                                                     --Receiving Clock
        signal tClk     :  std_logic;                                                                   --Transfering Clock
        signal dataCtr :  std_logic_vector(3 downto 0)   := "0000";              --Counts the number of read data bits
        signal parError:  std_logic;                                                                    --Parity error bit
        signal frameError: std_logic;                                                                   --Frame error bit
        signal CE               :  std_logic;                                                                   --Clock enable for the latch
        signal ctRst    :  std_logic := '0';
        signal load     :  std_logic := '0';
        signal shift    :  std_logic := '0';
        signal par      :  std_logic;
   signal tClkRST       :  std_logic := '0';
        signal rShift   :  std_logic := '0';
        signal dataRST :  std_logic := '0';
        signal dataIncr:  std_logic := '0';
 
        signal strCur   :  rstate       := strIdle;                             --Current state in the Receive state machine
        signal strNext  :  rstate;                                                                      --Next state in the Receive state machine
        signal sttCur  :  tstate := sttIdle;                                    --Current state in the Transfer state machine
        signal sttNext :  tstate;                                                                       --Next state in the Transfer staet machine
        signal stbeCur :  TBEstate := stbeIdle;
        signal stbeNext:  TBEstate;
 
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
 
begin
        frameError <= not rdSReg(9);
        parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
        DBOUT <= rdReg;
        tfReg <= DBIN;
        par <=  not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
 
--Clock Dividing Functions--
 
        process (CLK, clkDiv)                                                   --set up clock divide for rClk
                begin
                        if (Clk = '1' and Clk'event) then
                                if (clkDiv = baudDivide) then
                                        clkDiv <= "000000000";
                                else
                                        clkDiv <= clkDiv +1;
                                end if;
                        end if;
                end process;
 
        process (clkDiv, rClk, CLK)                                             --Define rClk
        begin
                if CLK = '1' and CLK'Event then
                        if clkDiv = baudDivide then
                                rClk <= not rClk;
                        else
                                rClk <= rClk;
                        end if;
                end if;
        end process;
 
        process (rClk)                                                                       --set up clock divide for tClk
                begin
                        if (rClk = '1' and rClk'event) then
                                rClkDiv <= rClkDiv +1;
                        end if;
                end process;
 
        tClk <= rClkDiv(3);                                                                     --define tClk
 
        process (rClk, ctRst)                                                   --set up a counter based on rClk
                begin
                        if rClk = '1' and rClk'Event then
                                if ctRst = '1' then
                                        ctr <= "0000";
                                else
                                        ctr <= ctr +1;
                                end if;
                        end if;
                end process;
 
        process (tClk, tClkRST)                                                         --set up a counter based on tClk
                begin
                        if (tClk = '1' and tClk'event) then
                                if tClkRST = '1' then
                                        tfCtr <= "0000";
                                else
                                        tfCtr <= tfCtr +1;
                                end if;
                        end if;
                end process;
 
        --This process controls the error flags--
        process (rClk, RST, RD, CE)
                begin
                        if RD = '1' or RST = '1' then
                                FE <= '0';
                                OE <= '0';
                                RDA <= '0';
                                PE <= '0';
                        elsif rClk = '1' and rClk'event then
                                if CE = '1' then
                                        FE <= frameError;
                                        OE <= RDA;
                                        RDA <= '1';
                                        PE <= parError;
                                        rdReg(7 downto 0) <= rdSReg (7 downto 0);
                                end if;
                        end if;
                end process;
 
        --This process controls the receiving shift register--
        process (rClk, rShift)
                begin
                        if rClk = '1' and rClk'Event then
                                if rShift = '1' then
                                        rdSReg <= (RXD & rdSReg(9 downto 1));
                                end if;
                        end if;
                end process;
 
        --This process controls the dataCtr to keep track of shifted values--
        process (rClk, dataRST)
                begin
                        if (rClk = '1' and rClk'event) then
                                if dataRST = '1' then
                                        dataCtr <= "0000";
                                elsif dataIncr = '1' then
                                        dataCtr <= dataCtr +1;
                                end if;
                        end if;
                end process;
 
        --Receiving State Machine--
        process (rClk, RST)
                begin
                        if rClk = '1' and rClk'Event then
                                if RST = '1' then
                                        strCur <= strIdle;
                                else
                                        strCur <= strNext;
                                end if;
                        end if;
                end process;
 
        --This process generates the sequence of steps needed receive the data
 
        process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
                begin
                        case strCur is
 
                                when strIdle =>
                                        dataIncr <= '0';
                                        rShift <= '0';
                                        dataRst <= '0';
 
                                        CE <= '0';
                                        if RXD = '0' then
                                                ctRst <= '1';
                                                strNext <= strEightDelay;
                                        else
                                                ctRst <= '0';
                                                strNext <= strIdle;
                                        end if;
 
                                when strEightDelay =>
                                        dataIncr <= '0';
                                        rShift <= '0';
                                        CE <= '0';
 
                                        if ctr(2 downto 0) = "111" then
                                                ctRst <= '1';
                                                dataRST <= '1';
                                                strNext <= strGetData;
                                        else
                                                ctRst <= '0';
                                                dataRST <= '0';
                                                strNext <= strEightDelay;
                                        end if;
 
                                when strGetData =>
                                        CE <= '0';
                                        dataRst <= '0';
                                        if ctr(3 downto 0) = "1111" then
                                                ctRst <= '1';
                                                dataIncr <= '1';
                                                rShift <= '1';
                                        else
                                                ctRst <= '0';
                                                dataIncr <= '0';
                                                rShift <= '0';
                                        end if;
 
                                        if dataCtr = "1010" then
                                                strNext <= strCheckStop;
                                        else
                                                strNext <= strGetData;
                                        end if;
 
                                when strCheckStop =>
                                        dataIncr <= '0';
                                        rShift <= '0';
                                        dataRst <= '0';
                                        ctRst <= '0';
 
                                        CE <= '1';
                                        strNext <= strIdle;
 
                        end case;
 
                end process;
 
        --TBE State Machine--
        process (CLK, RST)
                begin
                        if CLK = '1' and CLK'Event then
                                if RST = '1' then
                                        stbeCur <= stbeIdle;
                                else
                                        stbeCur <= stbeNext;
                                end if;
                        end if;
                end process;
 
        --This process gererates the sequence of events needed to control the TBE flag--
        process (stbeCur, CLK, WR, DBIN, load)
                begin
 
                        case stbeCur is
 
                                when stbeIdle =>
                                        TBE <= '1';
                                        if WR = '1' then
                                                stbeNext <= stbeSetTBE;
                                        else
                                                stbeNext <= stbeIdle;
                                        end if;
 
                                when stbeSetTBE =>
                                        TBE <= '0';
                                        if load = '1' then
                                                stbeNext <= stbeWaitLoad;
                                        else
                                                stbeNext <= stbeSetTBE;
                                        end if;
 
                                when stbeWaitLoad =>
                                        if load = '0' then
                                                stbeNext <= stbeWaitWrite;
                                        else
                                                stbeNext <= stbeWaitLoad;
                                        end if;
 
                                when stbeWaitWrite =>
                                        if WR = '0' then
                                                stbeNext <= stbeIdle;
                                        else
                                                stbeNext <= stbeWaitWrite;
                                        end if;
                                end case;
                        end process;
 
        --This process loads and shifts out the transfer shift register--
        process (load, shift, tClk, tfSReg)
                begin
                        TXD <= tfsReg(0);
                        if tClk = '1' and tClk'Event then
                                if load = '1' then
                                        tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
                                end if;
                                if shift = '1' then
 
                                        tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
                                end if;
                        end if;
                end process;
 
        --  Transfer State Machine--
        process (tClk, RST)
                begin
                        if (tClk = '1' and tClk'Event) then
                                if RST = '1' then
                                        sttCur <= sttIdle;
                                else
                                        sttCur <= sttNext;
                                end if;
                        end if;
                end process;
 
        --  This process generates the sequence of steps needed transfer the data--
        process (sttCur, tfCtr, tfReg, TBE, tclk)
                begin
 
                        case sttCur is
 
                                when sttIdle =>
                                        tClkRST <= '0';
                                        shift <= '0';
                                        load <= '0';
                                        if TBE = '1' then
                                                sttNext <= sttIdle;
                                        else
                                                sttNext <= sttTransfer;
                                        end if;
 
                                when sttTransfer =>
                                        shift <= '0';
                                        load <= '1';
                                        tClkRST <= '1';
                                        sttNext <= sttShift;
 
 
                                when sttShift =>
                                        shift <= '1';
                                        load <= '0';
                                        tClkRST <= '0';
                                        if tfCtr = "1100" then
                                                sttNext <= sttIdle;
                                        else
                                                sttNext <= sttShift;
                                        end if;
                        end case;
                end process;
 
end Behavioral;

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[/] [present/] [trunk/] [DecodeTesting/] [rtl/] [vhdl/] [RS232RefComp.vhd] - Blame information for rev 20

Line No.	Rev	Author	Line
1	3	gajos	`------------------------------------------------------------------------`
2			`-- RS232RefCom.vhd`
3			`------------------------------------------------------------------------`
4			`-- Author: Dan Pederson`
5			`-- Copyright 2004 Digilent, Inc.`
6			`------------------------------------------------------------------------`
7			`-- Description: This file defines a UART which tranfers data from`
8			`-- serial form to parallel form and vice versa.`
9			`------------------------------------------------------------------------`
10			`-- Revision History:`
11			`-- 07/15/04 (Created) DanP`
12			`-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant`
13			`-- in the Clock Dividing Processes`
14			`------------------------------------------------------------------------`
15
16			`library IEEE;`
17			`use IEEE.STD_LOGIC_1164.ALL;`
18			`use IEEE.STD_LOGIC_ARITH.ALL;`
19			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
20
21			`-- Uncomment the following lines to use the declarations that are`
22			`-- provided for instantiating Xilinx primitive components.`
23			`--library UNISIM;`
24			`--use UNISIM.VComponents.all;`
25
26			`entity Rs232RefComp is`
27			`Port (`
28			`TXD : out std_logic := '1';`
29			`RXD : in std_logic;`
30			`CLK : in std_logic; --Master Clock`
31			`DBIN : in std_logic_vector (7 downto 0); --Data Bus in`
32			`DBOUT : out std_logic_vector (7 downto 0); --Data Bus out`
33			`RDA : inout std_logic; --Read Data Available`
34			`TBE : inout std_logic := '1'; --Transfer Bus Empty`
35			`RD : in std_logic; --Read Strobe`
36			`WR : in std_logic; --Write Strobe`
37			`PE : out std_logic; --Parity Error Flag`
38			`FE : out std_logic; --Frame Error Flag`
39			`OE : out std_logic; --Overwrite Error Flag`
40			`RST : in std_logic := '0'); --Master Reset`
41			`end Rs232RefComp;`
42
43			`architecture Behavioral of Rs232RefComp is`
44			`------------------------------------------------------------------------`
45			`-- Component Declarations`
46			`------------------------------------------------------------------------`
47
48			`------------------------------------------------------------------------`
49			`-- Local Type Declarations`
50			`------------------------------------------------------------------------`
51			`--Receive state machine`
52			`type rstate is (`
53			`strIdle, --Idle state`
54			`strEightDelay, --Delays for 8 clock cycles`
55			`strGetData, --Shifts in the 8 data bits, and checks parity`
56			`strCheckStop --Sets framing error flag if Stop bit is wrong`
57			`);`
58
59			`type tstate is (`
60			`sttIdle, --Idle state`
61			`sttTransfer, --Move data into shift register`
62			`sttShift --Shift out data`
63			`);`
64
65			`type TBEstate is (`
66			`stbeIdle,`
67			`stbeSetTBE,`
68			`stbeWaitLoad,`
69			`stbeWaitWrite`
70			`);`
71
72
73			`------------------------------------------------------------------------`
74			`-- Signal Declarations`
75			`------------------------------------------------------------------------`
76			`constant baudDivide : std_logic_vector(7 downto 0) := "00001101"; --Baud Rate dividor, set now for a rate of 9600.`
77			`--Found by dividing 50MHz by 9600 and 16.`
78			`signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register`
79			`signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register`
80			`signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register`
81			`signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register`
82			`signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk`
83			`signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk`
84			`signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times`
85			`signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer`
86			`signal rClk : std_logic := '0'; --Receiving Clock`
87			`signal tClk : std_logic; --Transfering Clock`
88			`signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits`
89			`signal parError: std_logic; --Parity error bit`
90			`signal frameError: std_logic; --Frame error bit`
91			`signal CE : std_logic; --Clock enable for the latch`
92			`signal ctRst : std_logic := '0';`
93			`signal load : std_logic := '0';`
94			`signal shift : std_logic := '0';`
95			`signal par : std_logic;`
96			`signal tClkRST : std_logic := '0';`
97			`signal rShift : std_logic := '0';`
98			`signal dataRST : std_logic := '0';`
99			`signal dataIncr: std_logic := '0';`
100
101			`signal strCur : rstate := strIdle; --Current state in the Receive state machine`
102			`signal strNext : rstate; --Next state in the Receive state machine`
103			`signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine`
104			`signal sttNext : tstate; --Next state in the Transfer staet machine`
105			`signal stbeCur : TBEstate := stbeIdle;`
106			`signal stbeNext: TBEstate;`
107
108			`------------------------------------------------------------------------`
109			`-- Module Implementation`
110			`------------------------------------------------------------------------`
111
112			`begin`
113			`frameError <= not rdSReg(9);`
114			`parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );`
115			`DBOUT <= rdReg;`
116			`tfReg <= DBIN;`
117			`par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );`
118
119			`--Clock Dividing Functions--`
120
121			`process (CLK, clkDiv) --set up clock divide for rClk`
122			`begin`
123			`if (Clk = '1' and Clk'event) then`
124			`if (clkDiv = baudDivide) then`
125			`clkDiv <= "000000000";`
126			`else`
127			`clkDiv <= clkDiv +1;`
128			`end if;`
129			`end if;`
130			`end process;`
131
132			`process (clkDiv, rClk, CLK) --Define rClk`
133			`begin`
134			`if CLK = '1' and CLK'Event then`
135			`if clkDiv = baudDivide then`
136			`rClk <= not rClk;`
137			`else`
138			`rClk <= rClk;`
139			`end if;`
140			`end if;`
141			`end process;`
142
143			`process (rClk) --set up clock divide for tClk`
144			`begin`
145			`if (rClk = '1' and rClk'event) then`
146			`rClkDiv <= rClkDiv +1;`
147			`end if;`
148			`end process;`
149
150			`tClk <= rClkDiv(3); --define tClk`
151
152			`process (rClk, ctRst) --set up a counter based on rClk`
153			`begin`
154			`if rClk = '1' and rClk'Event then`
155			`if ctRst = '1' then`
156			`ctr <= "0000";`
157			`else`
158			`ctr <= ctr +1;`
159			`end if;`
160			`end if;`
161			`end process;`
162
163			`process (tClk, tClkRST) --set up a counter based on tClk`
164			`begin`
165			`if (tClk = '1' and tClk'event) then`
166			`if tClkRST = '1' then`
167			`tfCtr <= "0000";`
168			`else`
169			`tfCtr <= tfCtr +1;`
170			`end if;`
171			`end if;`
172			`end process;`
173
174			`--This process controls the error flags--`
175			`process (rClk, RST, RD, CE)`
176			`begin`
177			`if RD = '1' or RST = '1' then`
178			`FE <= '0';`
179			`OE <= '0';`
180			`RDA <= '0';`
181			`PE <= '0';`
182			`elsif rClk = '1' and rClk'event then`
183			`if CE = '1' then`
184			`FE <= frameError;`
185			`OE <= RDA;`
186			`RDA <= '1';`
187			`PE <= parError;`
188			`rdReg(7 downto 0) <= rdSReg (7 downto 0);`
189			`end if;`
190			`end if;`
191			`end process;`
192
193			`--This process controls the receiving shift register--`
194			`process (rClk, rShift)`
195			`begin`
196			`if rClk = '1' and rClk'Event then`
197			`if rShift = '1' then`
198			`rdSReg <= (RXD & rdSReg(9 downto 1));`
199			`end if;`
200			`end if;`
201			`end process;`
202
203			`--This process controls the dataCtr to keep track of shifted values--`
204			`process (rClk, dataRST)`
205			`begin`
206			`if (rClk = '1' and rClk'event) then`
207			`if dataRST = '1' then`
208			`dataCtr <= "0000";`
209			`elsif dataIncr = '1' then`
210			`dataCtr <= dataCtr +1;`
211			`end if;`
212			`end if;`
213			`end process;`
214
215			`--Receiving State Machine--`
216			`process (rClk, RST)`
217			`begin`
218			`if rClk = '1' and rClk'Event then`
219			`if RST = '1' then`
220			`strCur <= strIdle;`
221			`else`
222			`strCur <= strNext;`
223			`end if;`
224			`end if;`
225			`end process;`
226
227			`--This process generates the sequence of steps needed receive the data`
228
229			`process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)`
230			`begin`
231			`case strCur is`
232
233			`when strIdle =>`
234			`dataIncr <= '0';`
235			`rShift <= '0';`
236			`dataRst <= '0';`
237
238			`CE <= '0';`
239			`if RXD = '0' then`
240			`ctRst <= '1';`
241			`strNext <= strEightDelay;`
242			`else`
243			`ctRst <= '0';`
244			`strNext <= strIdle;`
245			`end if;`
246
247			`when strEightDelay =>`
248			`dataIncr <= '0';`
249			`rShift <= '0';`
250			`CE <= '0';`
251
252			`if ctr(2 downto 0) = "111" then`
253			`ctRst <= '1';`
254			`dataRST <= '1';`
255			`strNext <= strGetData;`
256			`else`
257			`ctRst <= '0';`
258			`dataRST <= '0';`
259			`strNext <= strEightDelay;`
260			`end if;`
261
262			`when strGetData =>`
263			`CE <= '0';`
264			`dataRst <= '0';`
265			`if ctr(3 downto 0) = "1111" then`
266			`ctRst <= '1';`
267			`dataIncr <= '1';`
268			`rShift <= '1';`
269			`else`
270			`ctRst <= '0';`
271			`dataIncr <= '0';`
272			`rShift <= '0';`
273			`end if;`
274
275			`if dataCtr = "1010" then`
276			`strNext <= strCheckStop;`
277			`else`
278			`strNext <= strGetData;`
279			`end if;`
280
281			`when strCheckStop =>`
282			`dataIncr <= '0';`
283			`rShift <= '0';`
284			`dataRst <= '0';`
285			`ctRst <= '0';`
286
287			`CE <= '1';`
288			`strNext <= strIdle;`
289
290			`end case;`
291
292			`end process;`
293
294			`--TBE State Machine--`
295			`process (CLK, RST)`
296			`begin`
297			`if CLK = '1' and CLK'Event then`
298			`if RST = '1' then`
299			`stbeCur <= stbeIdle;`
300			`else`
301			`stbeCur <= stbeNext;`
302			`end if;`
303			`end if;`
304			`end process;`
305
306			`--This process gererates the sequence of events needed to control the TBE flag--`
307			`process (stbeCur, CLK, WR, DBIN, load)`
308			`begin`
309
310			`case stbeCur is`
311
312			`when stbeIdle =>`
313			`TBE <= '1';`
314			`if WR = '1' then`
315			`stbeNext <= stbeSetTBE;`
316			`else`
317			`stbeNext <= stbeIdle;`
318			`end if;`
319
320			`when stbeSetTBE =>`
321			`TBE <= '0';`
322			`if load = '1' then`
323			`stbeNext <= stbeWaitLoad;`
324			`else`
325			`stbeNext <= stbeSetTBE;`
326			`end if;`
327
328			`when stbeWaitLoad =>`
329			`if load = '0' then`
330			`stbeNext <= stbeWaitWrite;`
331			`else`
332			`stbeNext <= stbeWaitLoad;`
333			`end if;`
334
335			`when stbeWaitWrite =>`
336			`if WR = '0' then`
337			`stbeNext <= stbeIdle;`
338			`else`
339			`stbeNext <= stbeWaitWrite;`
340			`end if;`
341			`end case;`
342			`end process;`
343
344			`--This process loads and shifts out the transfer shift register--`
345			`process (load, shift, tClk, tfSReg)`
346			`begin`
347			`TXD <= tfsReg(0);`
348			`if tClk = '1' and tClk'Event then`
349			`if load = '1' then`
350			`tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');`
351			`end if;`
352			`if shift = '1' then`
353
354			`tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));`
355			`end if;`
356			`end if;`
357			`end process;`
358
359			`-- Transfer State Machine--`
360			`process (tClk, RST)`
361			`begin`
362			`if (tClk = '1' and tClk'Event) then`
363			`if RST = '1' then`
364			`sttCur <= sttIdle;`
365			`else`
366			`sttCur <= sttNext;`
367			`end if;`
368			`end if;`
369			`end process;`
370
371			`-- This process generates the sequence of steps needed transfer the data--`
372			`process (sttCur, tfCtr, tfReg, TBE, tclk)`
373			`begin`
374
375			`case sttCur is`
376
377			`when sttIdle =>`
378			`tClkRST <= '0';`
379			`shift <= '0';`
380			`load <= '0';`
381			`if TBE = '1' then`
382			`sttNext <= sttIdle;`
383			`else`
384			`sttNext <= sttTransfer;`
385			`end if;`
386
387			`when sttTransfer =>`
388			`shift <= '0';`
389			`load <= '1';`
390			`tClkRST <= '1';`
391			`sttNext <= sttShift;`
392
393
394			`when sttShift =>`
395			`shift <= '1';`
396			`load <= '0';`
397			`tClkRST <= '0';`
398			`if tfCtr = "1100" then`
399			`sttNext <= sttIdle;`
400			`else`
401			`sttNext <= sttShift;`
402			`end if;`
403			`end case;`
404			`end process;`
405
406			`end Behavioral;`