| 1 |
4 |
gajos |
-----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- Present - a lightweight block cipher project ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the Present - a lightweight block ----
|
| 6 |
|
|
---- cipher project ----
|
| 7 |
|
|
---- http://www.http://opencores.org/project,present ----
|
| 8 |
|
|
---- ----
|
| 9 |
|
|
---- Description: ----
|
| 10 |
|
|
---- Shift register with parallel input/output. Nothing special----
|
| 11 |
|
|
---- except configuration - it enables wider input than output and ----
|
| 12 |
|
|
---- inverse config. ----
|
| 13 |
|
|
---- To Do: ----
|
| 14 |
|
|
---- ----
|
| 15 |
|
|
---- Author(s): ----
|
| 16 |
|
|
---- - Krzysztof Gajewski, gajos@opencores.org ----
|
| 17 |
|
|
---- k.gajewski@gmail.com ----
|
| 18 |
|
|
---- ----
|
| 19 |
|
|
-----------------------------------------------------------------------
|
| 20 |
|
|
---- ----
|
| 21 |
|
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
|
| 22 |
|
|
---- ----
|
| 23 |
|
|
---- This source file may be used and distributed without ----
|
| 24 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 25 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 26 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 27 |
|
|
---- ----
|
| 28 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 29 |
|
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
| 30 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 31 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 32 |
|
|
---- later version. ----
|
| 33 |
|
|
---- ----
|
| 34 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 35 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 36 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 37 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 38 |
|
|
---- details. ----
|
| 39 |
|
|
---- ----
|
| 40 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 41 |
|
|
---- Public License along with this source; if not, download it ----
|
| 42 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 43 |
|
|
---- ----
|
| 44 |
|
|
-----------------------------------------------------------------------
|
| 45 |
3 |
gajos |
library IEEE;
|
| 46 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 47 |
|
|
|
| 48 |
|
|
-- Uncomment the following library declaration if using
|
| 49 |
|
|
-- arithmetic functions with Signed or Unsigned values
|
| 50 |
|
|
--use IEEE.NUMERIC_STD.ALL;
|
| 51 |
|
|
|
| 52 |
|
|
-- Uncomment the following library declaration if instantiating
|
| 53 |
|
|
-- any Xilinx primitives in this code.
|
| 54 |
|
|
--library UNISIM;
|
| 55 |
|
|
--use UNISIM.VComponents.all;
|
| 56 |
|
|
|
| 57 |
|
|
entity ShiftReg is
|
| 58 |
|
|
generic (
|
| 59 |
|
|
length_1 : integer := 8;
|
| 60 |
|
|
length_2 : integer := 64;
|
| 61 |
|
|
internal_data : integer := 64
|
| 62 |
|
|
);
|
| 63 |
|
|
port (
|
| 64 |
|
|
input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);
|
| 65 |
|
|
output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
|
| 66 |
|
|
en : in STD_LOGIC;
|
| 67 |
|
|
shift : in STD_LOGIC;
|
| 68 |
|
|
clk : in STD_LOGIC;
|
| 69 |
|
|
reset : in STD_LOGIC
|
| 70 |
|
|
);
|
| 71 |
|
|
end ShiftReg;
|
| 72 |
|
|
|
| 73 |
|
|
architecture Behavioral of ShiftReg is
|
| 74 |
|
|
|
| 75 |
|
|
signal data : STD_LOGIC_VECTOR(internal_data - 1 downto 0);
|
| 76 |
|
|
|
| 77 |
|
|
begin
|
| 78 |
|
|
reg : process (clk, reset, data)
|
| 79 |
|
|
begin
|
| 80 |
|
|
if (clk'event and clk = '1') then
|
| 81 |
|
|
if (reset = '1') then
|
| 82 |
|
|
data <= (others => '0');
|
| 83 |
|
|
elsif (en = '1') then
|
| 84 |
|
|
data(internal_data - 1 downto internal_data - length_1) <= input;
|
| 85 |
|
|
else
|
| 86 |
|
|
if (shift = '1') then
|
| 87 |
|
|
data <= '0' & data(internal_data - 1 downto 1);
|
| 88 |
|
|
end if;
|
| 89 |
|
|
end if;
|
| 90 |
|
|
end if;
|
| 91 |
|
|
output <= data(length_2 - 1 downto 0);
|
| 92 |
|
|
end process reg;
|
| 93 |
|
|
|
| 94 |
|
|
end Behavioral;
|
| 95 |
|
|
|
