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[/] [present/] [trunk/] [DecodeTesting/] [rtl/] [vhdl/] [keyupd.vhd] - Blame information for rev 4

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1 4 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Present - a lightweight block cipher project                  ----
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----                                                               ----
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---- This file is part of the Present - a lightweight block        ----
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---- cipher project                                                ----
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---- http://www.http://opencores.org/project,present               ----
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----                                                               ----
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---- Description:                                                  ----
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----     Key update module for present cipher it is 'signal        ----
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---- mixing' made by rotation left by 61 bits, using one s-box,    ----
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---- and output of the counter. For more information see           ----
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---- http://homes.esat.kuleuven.be/~abogdano/papers/               ----
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---- present_ches07.pdf                                            ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
47 3 gajos
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity keyupd is
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        generic(
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                w_80: integer := 80;
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                w_5 : integer := 5;
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                w_4 : integer := 4);
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        port(
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                key : in std_logic_vector(w_80-1 downto 0);
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                num : in std_logic_vector(w_5-1 downto 0);
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                keyout : out std_logic_vector(w_80-1 downto 0)
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        );
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end keyupd;
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architecture Behavioral of keyupd is
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        component slayer is
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                generic(w_4: integer := 4);
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                port(
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                        input : in std_logic_vector(w_4-1 downto 0);
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                        output : out std_logic_vector(w_4-1 downto 0)
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                );
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        end component;
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        signal changed : std_logic_vector(w_4-1 downto 0);
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        signal changin : std_logic_vector(w_4-1 downto 0);
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        signal keytemp : std_logic_vector(w_80-1 downto 0);
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        begin
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                s1: slayer port map(input => changin, output => changed);
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                changin <= keytemp(79 downto 76);
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                keytemp <= key(18 downto 0) & key(79 downto 19);
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                keyout(79 downto 76)<= changed;
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                keyout(75 downto 20) <= keytemp(75 downto 20);
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                keyout(19 downto 15)<= keytemp(19 downto 15) xor num;
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                keyout(14 downto 0) <= keytemp(14 downto 0);
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        end Behavioral;

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