OpenCores
URL https://opencores.org/ocsvn/present/present/trunk

Subversion Repositories present

[/] [present/] [trunk/] [Pure/] [rtl/] [vhdl/] [PresentEnc.vhd] - Blame information for rev 13

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 gajos 
-----------------------------------------------------------------------
2 
----                                                               ----
3 
---- Present - a lightweight block cipher project                  ----
4 
----                                                               ----
5 
---- This file is part of the Present - a lightweight block        ----
6 
---- cipher project                                                ----
7 
---- http://www.http://opencores.org/project,present               ----
8 
----                                                               ----
9 
---- Description:                                                  ----
10 
----     Top level of present encoder. For more information see    ----
11 
---- below and http://homes.esat.kuleuven.be/~abogdano/papers/     ----
12 
---- present_ches07.pdf                                            ----
13 
---- To Do:                                                        ----
14 
----                                                               ----
15 
---- Author(s):                                                    ----
16 
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
17 
----                       k.gajewski@gmail.com                    ----
18 
----                                                               ----
19 
-----------------------------------------------------------------------
20 
----                                                               ----
21 
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
22 
----                                                               ----
23 
---- This source file may be used and distributed without          ----
24 
---- restriction provided that this copyright statement is not     ----
25 
---- removed from the file and that any derivative work contains   ----
26 
---- the original copyright notice and the associated disclaimer.  ----
27 
----                                                               ----
28 
---- This source file is free software; you can redistribute it    ----
29 
---- and-or modify it under the terms of the GNU Lesser General    ----
30 
---- Public License as published by the Free Software Foundation;  ----
31 
---- either version 2.1 of the License, or (at your option) any    ----
32 
---- later version.                                                ----
33 
----                                                               ----
34 
---- This source is distributed in the hope that it will be        ----
35 
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
36 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
37 
---- PURPOSE. See the GNU Lesser General Public License for more   ----
38 
---- details.                                                      ----
39 
----                                                               ----
40 
---- You should have received a copy of the GNU Lesser General     ----
41 
---- Public License along with this source; if not, download it    ----
42 
---- from http://www.opencores.org/lgpl.shtml                      ----
43 
----                                                               ----
44 
-----------------------------------------------------------------------
45 3 gajos 
library IEEE;
46 
use IEEE.STD_LOGIC_1164.ALL;
47 
use IEEE.STD_LOGIC_ARITH.ALL;
48 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
49 
use IEEE.NUMERIC_STD.ALL;
50 
 
51 
entity PresentEnc is
52 
        generic (
53 
                        w_2: integer := 2;
54 
                        w_4: integer := 4;
55 
                        w_5: integer := 5;
56 
                        w_32: integer := 32;
57 
                        w_64: integer := 64;
58 
                        w_80: integer := 80
59 
        );
60 
        port(
61 
                plaintext  : in std_logic_vector(w_64 - 1 downto 0);
62 
                key               : in std_logic_vector(w_80 - 1 downto 0);
63 
                ciphertext : out std_logic_vector(w_64 - 1 downto 0);
64 
                start, clk, reset : in std_logic;
65 
                ready : out std_logic
66 
        );
67 
end PresentEnc;
68 
 
69 
architecture Behavioral of PresentEnc is
70 
 
71 
        component Reg is
72 
                generic(width : integer := w_64);
73 
                port(
74 
                        input  : in  STD_LOGIC_VECTOR(width - 1 downto 0);
75 
                        output : out STD_LOGIC_VECTOR(width - 1 downto 0);
76 
                        enable : in  STD_LOGIC;
77 
                        clk    : in  STD_LOGIC;
78 
                        reset  : in  STD_LOGIC
79 
                );
80 
        end component Reg;
81 
 
82 
        component AsyncMux is
83 
                generic (
84 
                        width : integer := 64
85 
        );
86 
        port (
87 
                input0 : in  STD_LOGIC_VECTOR(width - 1 downto 0);
88 
                input1 : in  STD_LOGIC_VECTOR(width - 1 downto 0);
89 
                ctrl   : in  STD_LOGIC;
90 
                output : out STD_LOGIC_VECTOR(width - 1 downto 0)
91 
        );
92 
        end component AsyncMux;
93 
 
94 
        component PresentStateMachine is
95 
                generic (
96 
                        w_5 : integer := 5
97 
                );
98 
                port (
99 
                        clk, reset, start : in std_logic;
100 
                        ready, cnt_res, ctrl_mux, RegEn: out std_logic;
101 
                        num : in std_logic_vector (w_5-1 downto 0)
102 
                );
103 
        end component;
104 
 
105 4 gajos 
        -- substitution layer for decoding
106 3 gajos 
        component slayer is
107 
                generic (
108 
                                w_4 : integer := 4
109 
                );
110 
                port (
111 
                        input : in std_logic_vector(w_4-1 downto 0);
112 
                        output : out std_logic_vector(w_4-1 downto 0)
113 
                );
114 
        end component;
115 
 
116 4 gajos 
        -- permutation layer for decoding
117 3 gajos 
        component pLayer is
118 
                generic(w_64 : integer := 64);
119 
                port(
120 
                        input : in std_logic_vector(w_64-1 downto 0);
121 
                        output : out std_logic_vector(w_64-1 downto 0)
122 
                );
123 
        end component;
124 
 
125 4 gajos 
        -- key update for decoding
126 3 gajos 
        component keyupd is
127 
                generic(
128 
                        w_5 : integer := 5;
129 
                        w_80: integer := 80
130 
                );
131 
                port(
132 
                        num : in std_logic_vector(w_5-1 downto 0);
133 
                        key : in std_logic_vector(w_80-1 downto 0);
134 
                        keyout : out std_logic_vector(w_80-1 downto 0)
135 
                );
136 
        end component;
137 
 
138 4 gajos 
        -- counter for decoding. It is counting up!!!
139 3 gajos 
        component counter is
140 
                generic (
141 
                        w_5 : integer := 5
142 
                );
143 
                port (
144 
                        clk, reset, cnt_res : in std_logic;
145 
                        num : out std_logic_vector (w_5-1 downto 0)
146 
                );
147 
        end component;
148 
 
149 4 gajos 
        -- signals
150 
 
151 3 gajos 
        signal keynum : std_logic_vector (w_5-1 downto 0);
152 
        signal toXor, ciph, P, Pout, textToReg : std_logic_vector (w_64-1 downto 0);
153 
        signal keyfout, kupd, keyToReg : std_logic_vector (w_80-1 downto 0);
154 
        signal ready_sig, mux_ctrl,  cnt_res, RegEn : std_logic;
155 
 
156 
        begin
157 4 gajos 
 
158 
                -- connections
159 
 
160 3 gajos 
                mux_64: AsyncMux generic map(width => w_64) port map(
161 
                        input0 => plaintext,
162 
                        input1 => Pout,
163 
                        ctrl => mux_ctrl,
164 
                        output => textToReg
165 
                );
166 
                regText : Reg generic map(width => w_64) port map(
167 
                        input  => textToReg,
168 
                        output  => toXor,
169 
                        enable  => RegEn,
170 
                        clk  => clk,
171 
                        reset  => reset
172 
                );
173 
                mux_80: AsyncMux generic map(width => w_80) port map(
174 
                        input0 => key,
175 
                        input1 => kupd,
176 
                        ctrl => mux_ctrl,
177 
                        output => keyToReg
178 
                );
179 
                regKey : Reg generic map(width => w_80) port map(
180 
                        input  => keyToReg,
181 
                        output  => keyfout,
182 
                        enable  => RegEn,
183 
                        clk  => clk,
184 
                        reset  => reset
185 
                );
186 
                slayers : for N in 15 downto 0 generate
187 
                        s_x: slayer port map(
188 
                                input => ciph(4*N+3 downto 4*N),
189 
                                output => P(4*N+3 downto 4*N)
190 
                        );
191 
                end generate slayers;
192 
                p1: pLayer port map(
193 
                        input => P,
194 
                        output => Pout
195 
                );
196 
                mixer: keyupd port map(
197 
                        key => keyfout,
198 
                        num => keynum,
199 
                        keyout => kupd
200 
                );
201 
                SM: PresentStateMachine port map(
202 
                        start => start,
203 
                        reset => reset,
204 
                        ready => ready_sig,
205 
                        cnt_res => cnt_res,
206 
                        ctrl_mux => mux_ctrl,
207 
                        clk => clk,
208 
                        num => keynum,
209 
                        RegEn => RegEn
210 
                );
211 
                count: counter port map(
212 
                        clk => clk,
213 
                        reset => reset,
214 
                        cnt_res => cnt_res,
215 
                        num => keynum
216 
                );
217 
                ciph <= toXor xor keyfout(79 downto 16);
218 
                ciphertext <= ciph;
219 
                ready <= ready_sig;
220 
end Behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.