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[/] [present/] [trunk/] [PureTesting/] [bench/] [vhdl/] [PresentCommTB.vhd] - Blame information for rev 16

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-----------------------------------------------------------------------
----                                                               ----
---- Present - a lightweight block cipher project                  ----
----                                                               ----
---- This file is part of the Present - a lightweight block        ----
---- cipher project                                                ----
---- http://www.http://opencores.org/project,present               ----
----                                                               ----
---- Description:                                                  ----
----     This test bench simulate data transfer between PC and     ----
---- PresentComm core. All test data were generated in another     ----
---- program and textio was used for processing. Test bench is for ----
---- to distinct data sets.                                        ----
---- To Do:                                                        ----
----                                                               ----
---- Author(s):                                                    ----
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
----                       k.gajewski@gmail.com                    ----
----                                                               ----
-----------------------------------------------------------------------
----                                                               ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
----                                                               ----
---- This source file may be used and distributed without          ----
---- restriction provided that this copyright statement is not     ----
---- removed from the file and that any derivative work contains   ----
---- the original copyright notice and the associated disclaimer.  ----
----                                                               ----
---- This source file is free software; you can redistribute it    ----
---- and-or modify it under the terms of the GNU Lesser General    ----
---- Public License as published by the Free Software Foundation;  ----
---- either version 2.1 of the License, or (at your option) any    ----
---- later version.                                                ----
----                                                               ----
---- This source is distributed in the hope that it will be        ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
---- PURPOSE. See the GNU Lesser General Public License for more   ----
---- details.                                                      ----
----                                                               ----
---- You should have received a copy of the GNU Lesser General     ----
---- Public License along with this source; if not, download it    ----
---- from http://www.opencores.org/lgpl.shtml                      ----
----                                                               ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
USE work.txt_util.all;
USE ieee.std_logic_textio.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY PresentCommTB IS
END PresentCommTB;
 
ARCHITECTURE behavior OF PresentCommTB IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT PresentComm
    PORT(
         DATA_RXD : IN  std_logic;
         CLK : IN  std_logic;
         RESET : IN  std_logic;
         DATA_TXD : OUT  std_logic
        );
    END COMPONENT;
 
 
   --Inputs
   signal DATA_RXD : std_logic := '0';
   signal CLK : std_logic := '0';
   signal RESET : std_logic := '0';
 
        --Outputs
   signal DATA_TXD : std_logic;
 
   -- Clock period definitions
   -- speed of DIGILENT board and RS-232 core
   constant CLK_period : time := 20 ns;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: PresentComm PORT MAP (
          DATA_RXD => DATA_RXD,
          CLK => CLK,
          RESET => RESET,
          DATA_TXD => DATA_TXD
        );
 
   -- Clock process definitions
   CLK_process :process
   begin
                CLK <= '0';
                wait for CLK_period/2;
                CLK <= '1';
                wait for CLK_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
 
        -- Variables
        file txt :text is in "./test/data.txt";
        file key  :text is in "./test/key.txt";
        file txt2 :text is in "./test/data2.txt";
        file key2  :text is in "./test/key2.txt";
 
        variable line_in      : line;
        variable line_content : string(1 to 8);
        variable data         : STD_LOGIC;
 
   begin
 
                DATA_RXD <= '1';
                RESET <= '1';
      wait for 1000 ns;
                RESET <= '0';
 
      wait for CLK_period*10;
 
          -- All data are sent in direction from LSB to MSB
 
          -- Reading first 'data' file  each "segment" is one bit of serial data
      while not (endfile(txt)) loop
                        readline(txt, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        -- this amount is due to estimation of period of time needed for sending
                        -- one bit in RS-232 with 115 200 bps bandwith
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Reading first 'key' file  each "segment" is one bit of serial data
                while not (endfile(key)) loop
                        readline(key, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Cipher counting and sending result
                wait for 2000 us;
 
                -- Reading second 'data2' file  each "segment" is one bit of serial data
                while not (endfile(txt2)) loop
                        readline(txt2, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Reading second 'key2' file  each "segment" is one bit of serial data
                while not (endfile(key2)) loop
                        readline(key2, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Cipher counting and sending result
                wait for 2000 us;
 
      assert false severity failure;
   end process;
 
END;

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[/] [present/] [trunk/] [PureTesting/] [bench/] [vhdl/] [PresentCommTB.vhd] - Blame information for rev 16

Line No.	Rev	Author	Line
1	4	gajos	`-----------------------------------------------------------------------`
2			`---- ----`
3			`---- Present - a lightweight block cipher project ----`
4			`---- ----`
5			`---- This file is part of the Present - a lightweight block ----`
6			`---- cipher project ----`
7			`---- http://www.http://opencores.org/project,present ----`
8			`---- ----`
9			`---- Description: ----`
10			`---- This test bench simulate data transfer between PC and ----`
11			`---- PresentComm core. All test data were generated in another ----`
12			`---- program and textio was used for processing. Test bench is for ----`
13			`---- to distinct data sets. ----`
14			`---- To Do: ----`
15			`---- ----`
16			`---- Author(s): ----`
17			`---- - Krzysztof Gajewski, gajos@opencores.org ----`
18			`---- k.gajewski@gmail.com ----`
19			`---- ----`
20			`-----------------------------------------------------------------------`
21			`---- ----`
22			`---- Copyright (C) 2013 Authors and OPENCORES.ORG ----`
23			`---- ----`
24			`---- This source file may be used and distributed without ----`
25			`---- restriction provided that this copyright statement is not ----`
26			`---- removed from the file and that any derivative work contains ----`
27			`---- the original copyright notice and the associated disclaimer. ----`
28			`---- ----`
29			`---- This source file is free software; you can redistribute it ----`
30			`---- and-or modify it under the terms of the GNU Lesser General ----`
31			`---- Public License as published by the Free Software Foundation; ----`
32			`---- either version 2.1 of the License, or (at your option) any ----`
33			`---- later version. ----`
34			`---- ----`
35			`---- This source is distributed in the hope that it will be ----`
36			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
37			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
38			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
39			`---- details. ----`
40			`---- ----`
41			`---- You should have received a copy of the GNU Lesser General ----`
42			`---- Public License along with this source; if not, download it ----`
43			`---- from http://www.opencores.org/lgpl.shtml ----`
44			`---- ----`
45			`-----------------------------------------------------------------------`
46	3	gajos	`LIBRARY ieee;`
47			`USE ieee.std_logic_1164.ALL;`
48			`USE std.textio.all;`
49			`USE work.txt_util.all;`
50			`USE ieee.std_logic_textio.all;`
51
52			`-- Uncomment the following library declaration if using`
53			`-- arithmetic functions with Signed or Unsigned values`
54			`--USE ieee.numeric_std.ALL;`
55
56			`ENTITY PresentCommTB IS`
57			`END PresentCommTB;`
58
59			`ARCHITECTURE behavior OF PresentCommTB IS`
60
61			`-- Component Declaration for the Unit Under Test (UUT)`
62
63			`COMPONENT PresentComm`
64			`PORT(`
65			`DATA_RXD : IN std_logic;`
66			`CLK : IN std_logic;`
67			`RESET : IN std_logic;`
68			`DATA_TXD : OUT std_logic`
69			`);`
70			`END COMPONENT;`
71
72
73			`--Inputs`
74			`signal DATA_RXD : std_logic := '0';`
75			`signal CLK : std_logic := '0';`
76			`signal RESET : std_logic := '0';`
77
78			`--Outputs`
79			`signal DATA_TXD : std_logic;`
80
81			`-- Clock period definitions`
82	4	gajos	`-- speed of DIGILENT board and RS-232 core`
83	3	gajos	`constant CLK_period : time := 20 ns;`
84
85			`BEGIN`
86
87			`-- Instantiate the Unit Under Test (UUT)`
88			`uut: PresentComm PORT MAP (`
89			`DATA_RXD => DATA_RXD,`
90			`CLK => CLK,`
91			`RESET => RESET,`
92			`DATA_TXD => DATA_TXD`
93			`);`
94
95			`-- Clock process definitions`
96			`CLK_process :process`
97			`begin`
98			`CLK <= '0';`
99			`wait for CLK_period/2;`
100			`CLK <= '1';`
101			`wait for CLK_period/2;`
102			`end process;`
103
104
105			`-- Stimulus process`
106			`stim_proc: process`
107
108	4	gajos	`-- Variables`
109	13	gajos	`file txt :text is in "./test/data.txt";`
110			`file key :text is in "./test/key.txt";`
111			`file txt2 :text is in "./test/data2.txt";`
112			`file key2 :text is in "./test/key2.txt";`
113	3	gajos
114			`variable line_in : line;`
115			`variable line_content : string(1 to 8);`
116			`variable data : STD_LOGIC;`
117
118			`begin`
119
120			`DATA_RXD <= '1';`
121			`RESET <= '1';`
122			`wait for 1000 ns;`
123			`RESET <= '0';`
124
125			`wait for CLK_period*10;`
126
127	13	gajos	`-- All data are sent in direction from LSB to MSB`
128
129	4	gajos	`-- Reading first 'data' file each "segment" is one bit of serial data`
130	3	gajos	`while not (endfile(txt)) loop`
131			`readline(txt, line_in); -- info line`
132			`read(line_in, line_content);`
133			`report line_content;`
134
135	4	gajos	`DATA_RXD <= '0'; -- start bit`
136			`-- this amount is due to estimation of period of time needed for sending`
137			`-- one bit in RS-232 with 115 200 bps bandwith`
138	3	gajos	`wait for 8.75 us;`
139
140			`readline(txt, line_in);`
141			`read(line_in, data);`
142			`DATA_RXD <= data;`
143			`wait for 8.75 us;`
144
145			`readline(txt, line_in);`
146			`read(line_in, data);`
147			`DATA_RXD <= data;`
148			`wait for 8.75 us;`
149
150			`readline(txt, line_in);`
151			`read(line_in, data);`
152			`DATA_RXD <= data;`
153			`wait for 8.75 us;`
154
155			`readline(txt, line_in);`
156			`read(line_in, data);`
157			`DATA_RXD <= data;`
158			`wait for 8.75 us;`
159
160			`readline(txt, line_in);`
161			`read(line_in, data);`
162			`DATA_RXD <= data;`
163			`wait for 8.75 us;`
164
165			`readline(txt, line_in);`
166			`read(line_in, data);`
167			`DATA_RXD <= data;`
168			`wait for 8.75 us;`
169
170			`readline(txt, line_in);`
171			`read(line_in, data);`
172			`DATA_RXD <= data;`
173			`wait for 8.75 us;`
174
175			`readline(txt, line_in);`
176			`read(line_in, data);`
177			`DATA_RXD <= data;`
178			`wait for 8.75 us;`
179
180			`readline(txt, line_in);`
181			`read(line_in, data);`
182			`DATA_RXD <= data; -- parity bit`
183			`wait for 8.75 us;`
184
185	4	gajos	`report "End of byte";`
186	3	gajos	`DATA_RXD <= '1'; -- stop bit`
187			`wait for 100 us;`
188			`end loop;`
189
190	4	gajos	`-- Reading first 'key' file each "segment" is one bit of serial data`
191	3	gajos	`while not (endfile(key)) loop`
192			`readline(key, line_in); -- info line`
193			`read(line_in, line_content);`
194			`report line_content;`
195
196			`DATA_RXD <= '0'; -- start bit`
197			`wait for 8.75 us;`
198
199			`readline(key, line_in);`
200			`read(line_in, data);`
201			`DATA_RXD <= data;`
202			`wait for 8.75 us;`
203
204			`readline(key, line_in);`
205			`read(line_in, data);`
206			`DATA_RXD <= data;`
207			`wait for 8.75 us;`
208
209			`readline(key, line_in);`
210			`read(line_in, data);`
211			`DATA_RXD <= data;`
212			`wait for 8.75 us;`
213
214			`readline(key, line_in);`
215			`read(line_in, data);`
216			`DATA_RXD <= data;`
217			`wait for 8.75 us;`
218
219			`readline(key, line_in);`
220			`read(line_in, data);`
221			`DATA_RXD <= data;`
222			`wait for 8.75 us;`
223
224			`readline(key, line_in);`
225			`read(line_in, data);`
226			`DATA_RXD <= data;`
227			`wait for 8.75 us;`
228
229			`readline(key, line_in);`
230			`read(line_in, data);`
231			`DATA_RXD <= data;`
232			`wait for 8.75 us;`
233
234			`readline(key, line_in);`
235			`read(line_in, data);`
236			`DATA_RXD <= data;`
237			`wait for 8.75 us;`
238
239			`readline(key, line_in);`
240			`read(line_in, data);`
241			`DATA_RXD <= data; -- parity bit`
242			`wait for 8.75 us;`
243
244	4	gajos	`report "End of byte";`
245	3	gajos	`DATA_RXD <= '1'; -- stop bit`
246			`wait for 100 us;`
247			`end loop;`
248
249	4	gajos	`-- Cipher counting and sending result`
250	3	gajos	`wait for 2000 us;`
251
252	4	gajos	`-- Reading second 'data2' file each "segment" is one bit of serial data`
253	3	gajos	`while not (endfile(txt2)) loop`
254			`readline(txt2, line_in); -- info line`
255			`read(line_in, line_content);`
256			`report line_content;`
257
258			`DATA_RXD <= '0'; -- start bit`
259			`wait for 8.75 us;`
260
261			`readline(txt2, line_in);`
262			`read(line_in, data);`
263			`DATA_RXD <= data;`
264			`wait for 8.75 us;`
265
266			`readline(txt2, line_in);`
267			`read(line_in, data);`
268			`DATA_RXD <= data;`
269			`wait for 8.75 us;`
270
271			`readline(txt2, line_in);`
272			`read(line_in, data);`
273			`DATA_RXD <= data;`
274			`wait for 8.75 us;`
275
276			`readline(txt2, line_in);`
277			`read(line_in, data);`
278			`DATA_RXD <= data;`
279			`wait for 8.75 us;`
280
281			`readline(txt2, line_in);`
282			`read(line_in, data);`
283			`DATA_RXD <= data;`
284			`wait for 8.75 us;`
285
286			`readline(txt2, line_in);`
287			`read(line_in, data);`
288			`DATA_RXD <= data;`
289			`wait for 8.75 us;`
290
291			`readline(txt2, line_in);`
292			`read(line_in, data);`
293			`DATA_RXD <= data;`
294			`wait for 8.75 us;`
295
296			`readline(txt2, line_in);`
297			`read(line_in, data);`
298			`DATA_RXD <= data;`
299			`wait for 8.75 us;`
300
301			`readline(txt2, line_in);`
302			`read(line_in, data);`
303			`DATA_RXD <= data; -- parity bit`
304			`wait for 8.75 us;`
305
306	8	gajos	`report "End of byte";`
307	3	gajos	`DATA_RXD <= '1'; -- stop bit`
308			`wait for 100 us;`
309			`end loop;`
310
311	4	gajos	`-- Reading second 'key2' file each "segment" is one bit of serial data`
312	3	gajos	`while not (endfile(key2)) loop`
313			`readline(key2, line_in); -- info line`
314			`read(line_in, line_content);`
315			`report line_content;`
316
317			`DATA_RXD <= '0'; -- start bit`
318			`wait for 8.75 us;`
319
320			`readline(key2, line_in);`
321			`read(line_in, data);`
322			`DATA_RXD <= data;`
323			`wait for 8.75 us;`
324
325			`readline(key2, line_in);`
326			`read(line_in, data);`
327			`DATA_RXD <= data;`
328			`wait for 8.75 us;`
329
330			`readline(key2, line_in);`
331			`read(line_in, data);`
332			`DATA_RXD <= data;`
333			`wait for 8.75 us;`
334
335			`readline(key2, line_in);`
336			`read(line_in, data);`
337			`DATA_RXD <= data;`
338			`wait for 8.75 us;`
339
340			`readline(key2, line_in);`
341			`read(line_in, data);`
342			`DATA_RXD <= data;`
343			`wait for 8.75 us;`
344
345			`readline(key2, line_in);`
346			`read(line_in, data);`
347			`DATA_RXD <= data;`
348			`wait for 8.75 us;`
349
350			`readline(key2, line_in);`
351			`read(line_in, data);`
352			`DATA_RXD <= data;`
353			`wait for 8.75 us;`
354
355			`readline(key2, line_in);`
356			`read(line_in, data);`
357			`DATA_RXD <= data;`
358			`wait for 8.75 us;`
359
360			`readline(key2, line_in);`
361			`read(line_in, data);`
362			`DATA_RXD <= data; -- parity bit`
363			`wait for 8.75 us;`
364
365	8	gajos	`report "End of byte";`
366	3	gajos	`DATA_RXD <= '1'; -- stop bit`
367			`wait for 100 us;`
368			`end loop;`
369
370	4	gajos	`-- Cipher counting and sending result`
371	3	gajos	`wait for 2000 us;`
372
373			`assert false severity failure;`
374			`end process;`
375
376			`END;`