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[/] [present/] [trunk/] [PureTesting/] [bench/] [vhdl/] [PresentCommTB.vhd] - Blame information for rev 8

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-----------------------------------------------------------------------
----                                                               ----
---- Present - a lightweight block cipher project                  ----
----                                                               ----
---- This file is part of the Present - a lightweight block        ----
---- cipher project                                                ----
---- http://www.http://opencores.org/project,present               ----
----                                                               ----
---- Description:                                                  ----
----     This test bench simulate data transfer between PC and     ----
---- PresentComm core. All test data were generated in another     ----
---- program and textio was used for processing. Test bench is for ----
---- to distinct data sets.                                        ----
---- To Do:                                                        ----
----                                                               ----
---- Author(s):                                                    ----
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
----                       k.gajewski@gmail.com                    ----
----                                                               ----
-----------------------------------------------------------------------
----                                                               ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
----                                                               ----
---- This source file may be used and distributed without          ----
---- restriction provided that this copyright statement is not     ----
---- removed from the file and that any derivative work contains   ----
---- the original copyright notice and the associated disclaimer.  ----
----                                                               ----
---- This source file is free software; you can redistribute it    ----
---- and-or modify it under the terms of the GNU Lesser General    ----
---- Public License as published by the Free Software Foundation;  ----
---- either version 2.1 of the License, or (at your option) any    ----
---- later version.                                                ----
----                                                               ----
---- This source is distributed in the hope that it will be        ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
---- PURPOSE. See the GNU Lesser General Public License for more   ----
---- details.                                                      ----
----                                                               ----
---- You should have received a copy of the GNU Lesser General     ----
---- Public License along with this source; if not, download it    ----
---- from http://www.opencores.org/lgpl.shtml                      ----
----                                                               ----
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
USE work.txt_util.all;
USE ieee.std_logic_textio.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY PresentCommTB IS
END PresentCommTB;
 
ARCHITECTURE behavior OF PresentCommTB IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT PresentComm
    PORT(
         DATA_RXD : IN  std_logic;
         CLK : IN  std_logic;
         RESET : IN  std_logic;
         DATA_TXD : OUT  std_logic
        );
    END COMPONENT;
 
 
   --Inputs
   signal DATA_RXD : std_logic := '0';
   signal CLK : std_logic := '0';
   signal RESET : std_logic := '0';
 
        --Outputs
   signal DATA_TXD : std_logic;
 
   -- Clock period definitions
   -- speed of DIGILENT board and RS-232 core
   constant CLK_period : time := 20 ns;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: PresentComm PORT MAP (
          DATA_RXD => DATA_RXD,
          CLK => CLK,
          RESET => RESET,
          DATA_TXD => DATA_TXD
        );
 
   -- Clock process definitions
   CLK_process :process
   begin
                CLK <= '0';
                wait for CLK_period/2;
                CLK <= '1';
                wait for CLK_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
 
        -- Variables
        file txt :text is in "../src/test/data.txt";
        file key  :text is in "../src/test/key.txt";
        file txt2 :text is in "../src/test/data2.txt";
        file key2  :text is in "../src/test/key2.txt";
 
        variable line_in      : line;
        variable line_content : string(1 to 8);
        variable data         : STD_LOGIC;
 
   begin
 
                DATA_RXD <= '1';
                RESET <= '1';
      wait for 1000 ns;
                RESET <= '0';
 
      wait for CLK_period*10;
 
          -- Reading first 'data' file  each "segment" is one bit of serial data
      while not (endfile(txt)) loop
                        readline(txt, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        -- this amount is due to estimation of period of time needed for sending
                        -- one bit in RS-232 with 115 200 bps bandwith
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Reading first 'key' file  each "segment" is one bit of serial data
                while not (endfile(key)) loop
                        readline(key, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Cipher counting and sending result
                wait for 2000 us;
 
                -- Reading second 'data2' file  each "segment" is one bit of serial data
                while not (endfile(txt2)) loop
                        readline(txt2, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(txt2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Reading second 'key2' file  each "segment" is one bit of serial data
                while not (endfile(key2)) loop
                        readline(key2, line_in);  -- info line
                        read(line_in, line_content);
                        report line_content;
 
                        DATA_RXD <= '0'; -- start bit
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data;
                        wait for 8.75 us;
 
                        readline(key2, line_in);
                        read(line_in, data);
                        DATA_RXD <= data; -- parity bit
                        wait for 8.75 us;
 
                        report "End of byte";
                        DATA_RXD <= '1'; -- stop bit
                        wait for 100 us;
                end loop;
 
                -- Cipher counting and sending result
                wait for 2000 us;
 
      assert false severity failure;
   end process;
 
END;

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[/] [present/] [trunk/] [PureTesting/] [bench/] [vhdl/] [PresentCommTB.vhd] - Blame information for rev 8

Line No.	Rev	Author	Line
1	4	gajos	`-----------------------------------------------------------------------`
2			`---- ----`
3			`---- Present - a lightweight block cipher project ----`
4			`---- ----`
5			`---- This file is part of the Present - a lightweight block ----`
6			`---- cipher project ----`
7			`---- http://www.http://opencores.org/project,present ----`
8			`---- ----`
9			`---- Description: ----`
10			`---- This test bench simulate data transfer between PC and ----`
11			`---- PresentComm core. All test data were generated in another ----`
12			`---- program and textio was used for processing. Test bench is for ----`
13			`---- to distinct data sets. ----`
14			`---- To Do: ----`
15			`---- ----`
16			`---- Author(s): ----`
17			`---- - Krzysztof Gajewski, gajos@opencores.org ----`
18			`---- k.gajewski@gmail.com ----`
19			`---- ----`
20			`-----------------------------------------------------------------------`
21			`---- ----`
22			`---- Copyright (C) 2013 Authors and OPENCORES.ORG ----`
23			`---- ----`
24			`---- This source file may be used and distributed without ----`
25			`---- restriction provided that this copyright statement is not ----`
26			`---- removed from the file and that any derivative work contains ----`
27			`---- the original copyright notice and the associated disclaimer. ----`
28			`---- ----`
29			`---- This source file is free software; you can redistribute it ----`
30			`---- and-or modify it under the terms of the GNU Lesser General ----`
31			`---- Public License as published by the Free Software Foundation; ----`
32			`---- either version 2.1 of the License, or (at your option) any ----`
33			`---- later version. ----`
34			`---- ----`
35			`---- This source is distributed in the hope that it will be ----`
36			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
37			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
38			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
39			`---- details. ----`
40			`---- ----`
41			`---- You should have received a copy of the GNU Lesser General ----`
42			`---- Public License along with this source; if not, download it ----`
43			`---- from http://www.opencores.org/lgpl.shtml ----`
44			`---- ----`
45			`-----------------------------------------------------------------------`
46	3	gajos	`LIBRARY ieee;`
47			`USE ieee.std_logic_1164.ALL;`
48			`USE std.textio.all;`
49			`USE work.txt_util.all;`
50			`USE ieee.std_logic_textio.all;`
51
52			`-- Uncomment the following library declaration if using`
53			`-- arithmetic functions with Signed or Unsigned values`
54			`--USE ieee.numeric_std.ALL;`
55
56			`ENTITY PresentCommTB IS`
57			`END PresentCommTB;`
58
59			`ARCHITECTURE behavior OF PresentCommTB IS`
60
61			`-- Component Declaration for the Unit Under Test (UUT)`
62
63			`COMPONENT PresentComm`
64			`PORT(`
65			`DATA_RXD : IN std_logic;`
66			`CLK : IN std_logic;`
67			`RESET : IN std_logic;`
68			`DATA_TXD : OUT std_logic`
69			`);`
70			`END COMPONENT;`
71
72
73			`--Inputs`
74			`signal DATA_RXD : std_logic := '0';`
75			`signal CLK : std_logic := '0';`
76			`signal RESET : std_logic := '0';`
77
78			`--Outputs`
79			`signal DATA_TXD : std_logic;`
80
81			`-- Clock period definitions`
82	4	gajos	`-- speed of DIGILENT board and RS-232 core`
83	3	gajos	`constant CLK_period : time := 20 ns;`
84
85			`BEGIN`
86
87			`-- Instantiate the Unit Under Test (UUT)`
88			`uut: PresentComm PORT MAP (`
89			`DATA_RXD => DATA_RXD,`
90			`CLK => CLK,`
91			`RESET => RESET,`
92			`DATA_TXD => DATA_TXD`
93			`);`
94
95			`-- Clock process definitions`
96			`CLK_process :process`
97			`begin`
98			`CLK <= '0';`
99			`wait for CLK_period/2;`
100			`CLK <= '1';`
101			`wait for CLK_period/2;`
102			`end process;`
103
104
105			`-- Stimulus process`
106			`stim_proc: process`
107
108	4	gajos	`-- Variables`
109	8	gajos	`file txt :text is in "../src/test/data.txt";`
110			`file key :text is in "../src/test/key.txt";`
111			`file txt2 :text is in "../src/test/data2.txt";`
112			`file key2 :text is in "../src/test/key2.txt";`
113	3	gajos
114			`variable line_in : line;`
115			`variable line_content : string(1 to 8);`
116			`variable data : STD_LOGIC;`
117
118			`begin`
119
120			`DATA_RXD <= '1';`
121			`RESET <= '1';`
122			`wait for 1000 ns;`
123			`RESET <= '0';`
124
125			`wait for CLK_period*10;`
126
127	4	gajos	`-- Reading first 'data' file each "segment" is one bit of serial data`
128	3	gajos	`while not (endfile(txt)) loop`
129			`readline(txt, line_in); -- info line`
130			`read(line_in, line_content);`
131			`report line_content;`
132
133	4	gajos	`DATA_RXD <= '0'; -- start bit`
134			`-- this amount is due to estimation of period of time needed for sending`
135			`-- one bit in RS-232 with 115 200 bps bandwith`
136	3	gajos	`wait for 8.75 us;`
137
138			`readline(txt, line_in);`
139			`read(line_in, data);`
140			`DATA_RXD <= data;`
141			`wait for 8.75 us;`
142
143			`readline(txt, line_in);`
144			`read(line_in, data);`
145			`DATA_RXD <= data;`
146			`wait for 8.75 us;`
147
148			`readline(txt, line_in);`
149			`read(line_in, data);`
150			`DATA_RXD <= data;`
151			`wait for 8.75 us;`
152
153			`readline(txt, line_in);`
154			`read(line_in, data);`
155			`DATA_RXD <= data;`
156			`wait for 8.75 us;`
157
158			`readline(txt, line_in);`
159			`read(line_in, data);`
160			`DATA_RXD <= data;`
161			`wait for 8.75 us;`
162
163			`readline(txt, line_in);`
164			`read(line_in, data);`
165			`DATA_RXD <= data;`
166			`wait for 8.75 us;`
167
168			`readline(txt, line_in);`
169			`read(line_in, data);`
170			`DATA_RXD <= data;`
171			`wait for 8.75 us;`
172
173			`readline(txt, line_in);`
174			`read(line_in, data);`
175			`DATA_RXD <= data;`
176			`wait for 8.75 us;`
177
178			`readline(txt, line_in);`
179			`read(line_in, data);`
180			`DATA_RXD <= data; -- parity bit`
181			`wait for 8.75 us;`
182
183	4	gajos	`report "End of byte";`
184	3	gajos	`DATA_RXD <= '1'; -- stop bit`
185			`wait for 100 us;`
186			`end loop;`
187
188	4	gajos	`-- Reading first 'key' file each "segment" is one bit of serial data`
189	3	gajos	`while not (endfile(key)) loop`
190			`readline(key, line_in); -- info line`
191			`read(line_in, line_content);`
192			`report line_content;`
193
194			`DATA_RXD <= '0'; -- start bit`
195			`wait for 8.75 us;`
196
197			`readline(key, line_in);`
198			`read(line_in, data);`
199			`DATA_RXD <= data;`
200			`wait for 8.75 us;`
201
202			`readline(key, line_in);`
203			`read(line_in, data);`
204			`DATA_RXD <= data;`
205			`wait for 8.75 us;`
206
207			`readline(key, line_in);`
208			`read(line_in, data);`
209			`DATA_RXD <= data;`
210			`wait for 8.75 us;`
211
212			`readline(key, line_in);`
213			`read(line_in, data);`
214			`DATA_RXD <= data;`
215			`wait for 8.75 us;`
216
217			`readline(key, line_in);`
218			`read(line_in, data);`
219			`DATA_RXD <= data;`
220			`wait for 8.75 us;`
221
222			`readline(key, line_in);`
223			`read(line_in, data);`
224			`DATA_RXD <= data;`
225			`wait for 8.75 us;`
226
227			`readline(key, line_in);`
228			`read(line_in, data);`
229			`DATA_RXD <= data;`
230			`wait for 8.75 us;`
231
232			`readline(key, line_in);`
233			`read(line_in, data);`
234			`DATA_RXD <= data;`
235			`wait for 8.75 us;`
236
237			`readline(key, line_in);`
238			`read(line_in, data);`
239			`DATA_RXD <= data; -- parity bit`
240			`wait for 8.75 us;`
241
242	4	gajos	`report "End of byte";`
243	3	gajos	`DATA_RXD <= '1'; -- stop bit`
244			`wait for 100 us;`
245			`end loop;`
246
247	4	gajos	`-- Cipher counting and sending result`
248	3	gajos	`wait for 2000 us;`
249
250	4	gajos	`-- Reading second 'data2' file each "segment" is one bit of serial data`
251	3	gajos	`while not (endfile(txt2)) loop`
252			`readline(txt2, line_in); -- info line`
253			`read(line_in, line_content);`
254			`report line_content;`
255
256			`DATA_RXD <= '0'; -- start bit`
257			`wait for 8.75 us;`
258
259			`readline(txt2, line_in);`
260			`read(line_in, data);`
261			`DATA_RXD <= data;`
262			`wait for 8.75 us;`
263
264			`readline(txt2, line_in);`
265			`read(line_in, data);`
266			`DATA_RXD <= data;`
267			`wait for 8.75 us;`
268
269			`readline(txt2, line_in);`
270			`read(line_in, data);`
271			`DATA_RXD <= data;`
272			`wait for 8.75 us;`
273
274			`readline(txt2, line_in);`
275			`read(line_in, data);`
276			`DATA_RXD <= data;`
277			`wait for 8.75 us;`
278
279			`readline(txt2, line_in);`
280			`read(line_in, data);`
281			`DATA_RXD <= data;`
282			`wait for 8.75 us;`
283
284			`readline(txt2, line_in);`
285			`read(line_in, data);`
286			`DATA_RXD <= data;`
287			`wait for 8.75 us;`
288
289			`readline(txt2, line_in);`
290			`read(line_in, data);`
291			`DATA_RXD <= data;`
292			`wait for 8.75 us;`
293
294			`readline(txt2, line_in);`
295			`read(line_in, data);`
296			`DATA_RXD <= data;`
297			`wait for 8.75 us;`
298
299			`readline(txt2, line_in);`
300			`read(line_in, data);`
301			`DATA_RXD <= data; -- parity bit`
302			`wait for 8.75 us;`
303
304	8	gajos	`report "End of byte";`
305	3	gajos	`DATA_RXD <= '1'; -- stop bit`
306			`wait for 100 us;`
307			`end loop;`
308
309	4	gajos	`-- Reading second 'key2' file each "segment" is one bit of serial data`
310	3	gajos	`while not (endfile(key2)) loop`
311			`readline(key2, line_in); -- info line`
312			`read(line_in, line_content);`
313			`report line_content;`
314
315			`DATA_RXD <= '0'; -- start bit`
316			`wait for 8.75 us;`
317
318			`readline(key2, line_in);`
319			`read(line_in, data);`
320			`DATA_RXD <= data;`
321			`wait for 8.75 us;`
322
323			`readline(key2, line_in);`
324			`read(line_in, data);`
325			`DATA_RXD <= data;`
326			`wait for 8.75 us;`
327
328			`readline(key2, line_in);`
329			`read(line_in, data);`
330			`DATA_RXD <= data;`
331			`wait for 8.75 us;`
332
333			`readline(key2, line_in);`
334			`read(line_in, data);`
335			`DATA_RXD <= data;`
336			`wait for 8.75 us;`
337
338			`readline(key2, line_in);`
339			`read(line_in, data);`
340			`DATA_RXD <= data;`
341			`wait for 8.75 us;`
342
343			`readline(key2, line_in);`
344			`read(line_in, data);`
345			`DATA_RXD <= data;`
346			`wait for 8.75 us;`
347
348			`readline(key2, line_in);`
349			`read(line_in, data);`
350			`DATA_RXD <= data;`
351			`wait for 8.75 us;`
352
353			`readline(key2, line_in);`
354			`read(line_in, data);`
355			`DATA_RXD <= data;`
356			`wait for 8.75 us;`
357
358			`readline(key2, line_in);`
359			`read(line_in, data);`
360			`DATA_RXD <= data; -- parity bit`
361			`wait for 8.75 us;`
362
363	8	gajos	`report "End of byte";`
364	3	gajos	`DATA_RXD <= '1'; -- stop bit`
365			`wait for 100 us;`
366			`end loop;`
367
368	4	gajos	`-- Cipher counting and sending result`
369	3	gajos	`wait for 2000 us;`
370
371			`assert false severity failure;`
372			`end process;`
373
374			`END;`