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-----------------------------------------------------------------------
----                                                               ----
---- Present - a lightweight block cipher project                  ----
----                                                               ----
---- This file is part of the Present - a lightweight block        ----
---- cipher project                                                ----
---- http://www.http://opencores.org/project,present               ----
----                                                               ----
---- Description:                                                  ----
----     Top level part of 'pure' Present cipher with RS-232       ----
---- communication with PC. It contains all suitable components    ----
---- with links between each others. For more informations see     ----
---- below and http://homes.esat.kuleuven.be/~abogdano/papers/     ----
---- present_ches07.pdf                                            ----
---- To Do:                                                        ----
----                                                               ----
---- Author(s):                                                    ----
---- - Krzysztof Gajewski, gajos@opencores.org                     ----
----                       k.gajewski@gmail.com                    ----
----                                                               ----
-----------------------------------------------------------------------
----                                                               ----
---- Copyright (C) 2013 Authors and OPENCORES.ORG                  ----
----                                                               ----
---- This source file may be used and distributed without          ----
---- restriction provided that this copyright statement is not     ----
---- removed from the file and that any derivative work contains   ----
---- the original copyright notice and the associated disclaimer.  ----
----                                                               ----
---- This source file is free software; you can redistribute it    ----
---- and-or modify it under the terms of the GNU Lesser General    ----
---- Public License as published by the Free Software Foundation;  ----
---- either version 2.1 of the License, or (at your option) any    ----
---- later version.                                                ----
----                                                               ----
---- This source is distributed in the hope that it will be        ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
---- PURPOSE. See the GNU Lesser General Public License for more   ----
---- details.                                                      ----
----                                                               ----
---- You should have received a copy of the GNU Lesser General     ----
---- Public License along with this source; if not, download it    ----
---- from http://www.opencores.org/lgpl.shtml                      ----
----                                                               ----
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PresentComm is
        generic (
                        w_2: integer := 2;
                        w_4: integer := 4;
                        w_5: integer := 5;
                        w_64: integer := 64;
                        w_80: integer := 80
        );
        port (
                DATA_RXD : in  STD_LOGIC;
                CLK             : in  STD_LOGIC;
                RESET           : in  STD_LOGIC;
                DATA_TXD        : out STD_LOGIC
        );
end PresentComm;
 
architecture Behavioral of PresentComm is
 
-- Shift register is used for translation 8 bit input of RS-232 data (both RXD and TXD)
-- 64 bit and 80 bit data in dependence of the data type (key, text, result). SM ocntrols it
-- If data are not fully retrieved, last received data are shifted by 8 bits. This is repeated
-- 8 times for text and output value (8 x 8 bits) or 10 times (10 x 8 bits) for key.
-- Width of the word is fully configurable.
component ShiftReg is
        generic (
                length_1      : integer :=  8;
                length_2      : integer :=  w_64;
                internal_data : integer :=  w_64
        );
        port (
                input  : in  STD_LOGIC_VECTOR(length_1 - 1 downto 0);
                output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);
                en     : in  STD_LOGIC;
                shift  : in  STD_LOGIC;
                clk    : in  STD_LOGIC;
                reset  : in  STD_LOGIC
        );
end component ShiftReg;
 
-- Component given by Digilent in Eval board for RS-232 communication
component Rs232RefComp is
    Port (
                TXD     : out std_logic         := '1';
        RXD     : in  std_logic;
        CLK     : in  std_logic;                                                                --Master Clock
                DBIN    : in  std_logic_vector (7 downto 0);     --Data Bus in
                DBOUT : out std_logic_vector (7 downto 0);       --Data Bus out
                RDA     : inout std_logic;                                              --Read Data Available
                TBE     : inout std_logic       := '1';                 --Transfer Bus Empty
                RD              : in  std_logic;                                        --Read Strobe
                WR              : in  std_logic;                                        --Write Strobe
                PE              : out std_logic;                                        --Parity Error Flag
                FE              : out std_logic;                                        --Frame Error Flag
                OE              : out std_logic;                                        --Overwrite Error Flag
                RST             : in  std_logic := '0'); --Master Reset
end component Rs232RefComp;
 
-- Present cipher - nothing special
component PresentEnc is
        generic (
                w_64: integer := 64;
                w_80: integer := 80
        );
        port(
                plaintext                       : in std_logic_vector(w_64 - 1 downto 0);
                key                                     : in std_logic_vector(w_80 - 1 downto 0);
                ciphertext                      : out std_logic_vector(w_64 - 1 downto 0);
                start, clk, reset       : in std_logic;
                ready                           : out std_logic
        );
end component PresentEnc;
 
-- State machine
component PresentCommSM is
        port (
                clk                             : in STD_LOGIC;
                reset                           : in STD_LOGIC;
                RDAsig                  : in STD_LOGIC;
                TBEsig                  : in STD_LOGIC;
                RDsig                           : out STD_LOGIC;
                WRsig                           : out STD_LOGIC;
                textDataEn     : out STD_LOGIC;
                textDataShift   : out STD_LOGIC;
                keyDataEn               : out STD_LOGIC;
                keyDataShift    : out STD_LOGIC;
                ciphDataEn     : out STD_LOGIC;
                ciphDataShift  : out STD_LOGIC;
                startSig                        : out STD_LOGIC;
                readySig                        : in STD_LOGIC
        );
end component PresentCommSM;
 
--Signals
signal keyText    : STD_LOGIC_VECTOR(w_80 - 1 downto 0);
signal plaintext  : STD_LOGIC_VECTOR(w_64 - 1 downto 0);
signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);
 
signal dataTXD : STD_LOGIC_VECTOR(7 downto 0);
signal dataRXD : STD_LOGIC_VECTOR(7 downto 0);
signal RDAsig  : STD_LOGIC;
signal TBEsig  : STD_LOGIC;
signal RDsig   : STD_LOGIC;
signal WRsig   : STD_LOGIC;
signal PEsig   : STD_LOGIC;
signal FEsig   : STD_LOGIC;
signal OEsig   : STD_LOGIC;
 
signal keyDataEn    : STD_LOGIC;
signal keyDataShift : STD_LOGIC;
 
signal textDataEn    : STD_LOGIC;
signal textDataShift : STD_LOGIC;
 
signal ciphDataEn    : STD_LOGIC;
signal ciphDataShift : STD_LOGIC;
 
signal startSig : STD_LOGIC;
signal readySig : STD_LOGIC;
 
begin
    -- Connections
 
        RS232 : Rs232RefComp
                Port map(
                        TXD     => DATA_TXD,
                        RXD     => DATA_RXD,
                        CLK     => clk,
                        DBIN    => dataTXD,
                        DBOUT => dataRXD,
                        RDA     => RDAsig,
                        TBE     => TBEsig,
                        RD              => RDsig,
                        WR              => WRsig,
                        PE              => PEsig,
                        FE              => FEsig,
                        OE              => OEsig,
                        RST     => reset
                );
 
        textReg : ShiftReg
                generic map(
                        length_1 => 8,
                        length_2 => w_64,
                        internal_data => w_64
                )
                port map(
                        input  => dataRXD,
                        output => plaintext,
                        en     => textDataEn,
                        shift  => textDataShift,
                        clk    => clk,
                        reset  => reset
                );
 
        keyReg : ShiftReg
                generic map(
                        length_1 => 8,
                        length_2 => w_80,
                        internal_data => w_80
                )
                port map(
                        input  => dataRXD,
                        output => keyText,
                        en     => keyDataEn,
                        shift  => keyDataShift,
                        clk    => clk,
                        reset  => reset
                );
 
        present :PresentEnc
                port map(
                        plaintext       => plaintext,
                        key                     => keyText,
                        ciphertext      => ciphertext,
                        start                   => startSig,
                        clk                     => clk,
                        reset                   => reset,
                        ready                   => readySig
                );
 
        outReg : ShiftReg
                generic map(
                        length_1 => w_64,
                        length_2 => 8,
                        internal_data => w_64
                )
                port map(
                        input  => ciphertext,
                        output => dataTXD,
                        en     => ciphDataEn,
                        shift  => ciphDataShift,
                        clk    => clk,
                        reset  => reset
                );
 
        SM : PresentCommSM
                port map(
                        clk                             => clk,
                        reset                           => reset,
                        RDAsig                  => RDAsig,
                        TBEsig                  => TBEsig,
                        RDsig                           => RDsig,
                        WRsig                           => WRsig,
                        textDataEn     => textDataEn,
                        textDataShift   => textDataShift,
                        keyDataEn               => keyDataEn,
                        keyDataShift    => keyDataShift,
                        ciphDataEn     => ciphDataEn,
                        ciphDataShift  => ciphDataShift,
                        startSig                        => startSig,
                        readySig                        => readySig
                );
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	4	gajos	`-----------------------------------------------------------------------`
2			`---- ----`
3			`---- Present - a lightweight block cipher project ----`
4			`---- ----`
5			`---- This file is part of the Present - a lightweight block ----`
6			`---- cipher project ----`
7			`---- http://www.http://opencores.org/project,present ----`
8			`---- ----`
9			`---- Description: ----`
10			`---- Top level part of 'pure' Present cipher with RS-232 ----`
11			`---- communication with PC. It contains all suitable components ----`
12			`---- with links between each others. For more informations see ----`
13			`---- below and http://homes.esat.kuleuven.be/~abogdano/papers/ ----`
14			`---- present_ches07.pdf ----`
15			`---- To Do: ----`
16			`---- ----`
17			`---- Author(s): ----`
18			`---- - Krzysztof Gajewski, gajos@opencores.org ----`
19			`---- k.gajewski@gmail.com ----`
20			`---- ----`
21			`-----------------------------------------------------------------------`
22			`---- ----`
23			`---- Copyright (C) 2013 Authors and OPENCORES.ORG ----`
24			`---- ----`
25			`---- This source file may be used and distributed without ----`
26			`---- restriction provided that this copyright statement is not ----`
27			`---- removed from the file and that any derivative work contains ----`
28			`---- the original copyright notice and the associated disclaimer. ----`
29			`---- ----`
30			`---- This source file is free software; you can redistribute it ----`
31			`---- and-or modify it under the terms of the GNU Lesser General ----`
32			`---- Public License as published by the Free Software Foundation; ----`
33			`---- either version 2.1 of the License, or (at your option) any ----`
34			`---- later version. ----`
35			`---- ----`
36			`---- This source is distributed in the hope that it will be ----`
37			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
38			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
39			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
40			`---- details. ----`
41			`---- ----`
42			`---- You should have received a copy of the GNU Lesser General ----`
43			`---- Public License along with this source; if not, download it ----`
44			`---- from http://www.opencores.org/lgpl.shtml ----`
45			`---- ----`
46			`-----------------------------------------------------------------------`
47	3	gajos	`library IEEE;`
48			`use IEEE.STD_LOGIC_1164.ALL;`
49
50			`-- Uncomment the following library declaration if using`
51			`-- arithmetic functions with Signed or Unsigned values`
52			`--use IEEE.NUMERIC_STD.ALL;`
53
54			`-- Uncomment the following library declaration if instantiating`
55			`-- any Xilinx primitives in this code.`
56			`--library UNISIM;`
57			`--use UNISIM.VComponents.all;`
58
59			`entity PresentComm is`
60			`generic (`
61			`w_2: integer := 2;`
62			`w_4: integer := 4;`
63			`w_5: integer := 5;`
64			`w_64: integer := 64;`
65			`w_80: integer := 80`
66			`);`
67			`port (`
68			`DATA_RXD : in STD_LOGIC;`
69			`CLK : in STD_LOGIC;`
70			`RESET : in STD_LOGIC;`
71			`DATA_TXD : out STD_LOGIC`
72			`);`
73			`end PresentComm;`
74
75			`architecture Behavioral of PresentComm is`
76
77	4	gajos	`-- Shift register is used for translation 8 bit input of RS-232 data (both RXD and TXD)`
78			`-- 64 bit and 80 bit data in dependence of the data type (key, text, result). SM ocntrols it`
79			`-- If data are not fully retrieved, last received data are shifted by 8 bits. This is repeated`
80			`-- 8 times for text and output value (8 x 8 bits) or 10 times (10 x 8 bits) for key.`
81			`-- Width of the word is fully configurable.`
82	3	gajos	`component ShiftReg is`
83			`generic (`
84			`length_1 : integer := 8;`
85			`length_2 : integer := w_64;`
86			`internal_data : integer := w_64`
87			`);`
88			`port (`
89			`input : in STD_LOGIC_VECTOR(length_1 - 1 downto 0);`
90			`output : out STD_LOGIC_VECTOR(length_2 - 1 downto 0);`
91			`en : in STD_LOGIC;`
92			`shift : in STD_LOGIC;`
93			`clk : in STD_LOGIC;`
94			`reset : in STD_LOGIC`
95			`);`
96			`end component ShiftReg;`
97
98	4	gajos	`-- Component given by Digilent in Eval board for RS-232 communication`
99	3	gajos	`component Rs232RefComp is`
100			`Port (`
101			`TXD : out std_logic := '1';`
102			`RXD : in std_logic;`
103			`CLK : in std_logic; --Master Clock`
104			`DBIN : in std_logic_vector (7 downto 0); --Data Bus in`
105			`DBOUT : out std_logic_vector (7 downto 0); --Data Bus out`
106			`RDA : inout std_logic; --Read Data Available`
107			`TBE : inout std_logic := '1'; --Transfer Bus Empty`
108			`RD : in std_logic; --Read Strobe`
109			`WR : in std_logic; --Write Strobe`
110			`PE : out std_logic; --Parity Error Flag`
111			`FE : out std_logic; --Frame Error Flag`
112			`OE : out std_logic; --Overwrite Error Flag`
113			`RST : in std_logic := '0'); --Master Reset`
114			`end component Rs232RefComp;`
115
116	4	gajos	`-- Present cipher - nothing special`
117	3	gajos	`component PresentEnc is`
118			`generic (`
119			`w_64: integer := 64;`
120			`w_80: integer := 80`
121			`);`
122			`port(`
123			`plaintext : in std_logic_vector(w_64 - 1 downto 0);`
124			`key : in std_logic_vector(w_80 - 1 downto 0);`
125			`ciphertext : out std_logic_vector(w_64 - 1 downto 0);`
126			`start, clk, reset : in std_logic;`
127			`ready : out std_logic`
128			`);`
129			`end component PresentEnc;`
130
131	4	gajos	`-- State machine`
132	3	gajos	`component PresentCommSM is`
133			`port (`
134			`clk : in STD_LOGIC;`
135			`reset : in STD_LOGIC;`
136			`RDAsig : in STD_LOGIC;`
137			`TBEsig : in STD_LOGIC;`
138			`RDsig : out STD_LOGIC;`
139			`WRsig : out STD_LOGIC;`
140			`textDataEn : out STD_LOGIC;`
141			`textDataShift : out STD_LOGIC;`
142			`keyDataEn : out STD_LOGIC;`
143			`keyDataShift : out STD_LOGIC;`
144			`ciphDataEn : out STD_LOGIC;`
145			`ciphDataShift : out STD_LOGIC;`
146			`startSig : out STD_LOGIC;`
147			`readySig : in STD_LOGIC`
148			`);`
149			`end component PresentCommSM;`
150
151	4	gajos	`--Signals`
152	3	gajos	`signal keyText : STD_LOGIC_VECTOR(w_80 - 1 downto 0);`
153			`signal plaintext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);`
154			`signal ciphertext : STD_LOGIC_VECTOR(w_64 - 1 downto 0);`
155
156			`signal dataTXD : STD_LOGIC_VECTOR(7 downto 0);`
157			`signal dataRXD : STD_LOGIC_VECTOR(7 downto 0);`
158			`signal RDAsig : STD_LOGIC;`
159			`signal TBEsig : STD_LOGIC;`
160			`signal RDsig : STD_LOGIC;`
161			`signal WRsig : STD_LOGIC;`
162			`signal PEsig : STD_LOGIC;`
163			`signal FEsig : STD_LOGIC;`
164			`signal OEsig : STD_LOGIC;`
165
166			`signal keyDataEn : STD_LOGIC;`
167			`signal keyDataShift : STD_LOGIC;`
168
169			`signal textDataEn : STD_LOGIC;`
170			`signal textDataShift : STD_LOGIC;`
171
172			`signal ciphDataEn : STD_LOGIC;`
173			`signal ciphDataShift : STD_LOGIC;`
174
175			`signal startSig : STD_LOGIC;`
176			`signal readySig : STD_LOGIC;`
177
178			`begin`
179	4	gajos	`-- Connections`
180	3	gajos
181			`RS232 : Rs232RefComp`
182			`Port map(`
183			`TXD => DATA_TXD,`
184			`RXD => DATA_RXD,`
185			`CLK => clk,`
186			`DBIN => dataTXD,`
187			`DBOUT => dataRXD,`
188			`RDA => RDAsig,`
189			`TBE => TBEsig,`
190			`RD => RDsig,`
191			`WR => WRsig,`
192			`PE => PEsig,`
193			`FE => FEsig,`
194			`OE => OEsig,`
195			`RST => reset`
196			`);`
197
198			`textReg : ShiftReg`
199			`generic map(`
200			`length_1 => 8,`
201			`length_2 => w_64,`
202			`internal_data => w_64`
203			`)`
204			`port map(`
205			`input => dataRXD,`
206			`output => plaintext,`
207			`en => textDataEn,`
208			`shift => textDataShift,`
209			`clk => clk,`
210			`reset => reset`
211			`);`
212
213			`keyReg : ShiftReg`
214			`generic map(`
215			`length_1 => 8,`
216			`length_2 => w_80,`
217			`internal_data => w_80`
218			`)`
219			`port map(`
220			`input => dataRXD,`
221			`output => keyText,`
222			`en => keyDataEn,`
223			`shift => keyDataShift,`
224			`clk => clk,`
225			`reset => reset`
226			`);`
227
228			`present :PresentEnc`
229			`port map(`
230			`plaintext => plaintext,`
231			`key => keyText,`
232			`ciphertext => ciphertext,`
233			`start => startSig,`
234			`clk => clk,`
235			`reset => reset,`
236			`ready => readySig`
237			`);`
238
239			`outReg : ShiftReg`
240			`generic map(`
241			`length_1 => w_64,`
242			`length_2 => 8,`
243			`internal_data => w_64`
244			`)`
245			`port map(`
246			`input => ciphertext,`
247			`output => dataTXD,`
248			`en => ciphDataEn,`
249			`shift => ciphDataShift,`
250			`clk => clk,`
251			`reset => reset`
252			`);`
253
254			`SM : PresentCommSM`
255			`port map(`
256			`clk => clk,`
257			`reset => reset,`
258			`RDAsig => RDAsig,`
259			`TBEsig => TBEsig,`
260			`RDsig => RDsig,`
261			`WRsig => WRsig,`
262			`textDataEn => textDataEn,`
263			`textDataShift => textDataShift,`
264			`keyDataEn => keyDataEn,`
265			`keyDataShift => keyDataShift,`
266			`ciphDataEn => ciphDataEn,`
267			`ciphDataShift => ciphDataShift,`
268			`startSig => startSig,`
269			`readySig => readySig`
270			`);`
271
272			`end Behavioral;`
273

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[/] [present/] [trunk/] [PureTesting/] [rtl/] [vhdl/] [PresentComm.vhd] - Blame information for rev 4