| 1 |
21 |
rameli |
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
|
| 2 |
|
|
// Design Name: Key Update Procedure for Present Cipher //
|
| 3 |
|
|
// Module Name: key_update //
|
| 4 |
|
|
// Language: Verilog //
|
| 5 |
|
|
// Date Created: 1/16/2011 //
|
| 6 |
|
|
// Author: Reza Ameli //
|
| 7 |
|
|
// Digital Systems Lab //
|
| 8 |
|
|
// Ferdowsi University of Mashhad, Iran //
|
| 9 |
|
|
// http://commeng.um.ac.ir/dslab //
|
| 10 |
|
|
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
|
| 11 |
|
|
// //
|
| 12 |
|
|
// This source file may be used and distributed without //
|
| 13 |
|
|
// restriction provided that this copyright statement is not //
|
| 14 |
|
|
// removed from the file and that any derivative work contains //
|
| 15 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 16 |
|
|
// //
|
| 17 |
|
|
// This source file is free software; you can redistribute it //
|
| 18 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 19 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 20 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 21 |
|
|
// later version. //
|
| 22 |
|
|
// //
|
| 23 |
|
|
// This source is distributed in the hope that it will be //
|
| 24 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 25 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 26 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 27 |
|
|
// details. //
|
| 28 |
|
|
// //
|
| 29 |
|
|
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
|
| 30 |
|
|
|
| 31 |
|
|
module key_update(data_o,data_i,round_counter);
|
| 32 |
|
|
|
| 33 |
|
|
//- Module IOs ----------------------------------------------------------------
|
| 34 |
|
|
|
| 35 |
|
|
output wire[79 : 0] data_o; // 80-bit input
|
| 36 |
|
|
input wire[79 : 0] data_i; // 80-bit output (will be the updated value of current key)
|
| 37 |
|
|
input wire[4 : 0] round_counter;
|
| 38 |
|
|
|
| 39 |
|
|
//- Variables, Registers and Parameters ---------------------------------------
|
| 40 |
|
|
|
| 41 |
|
|
wire [79:0] s1,s2,s3; // intermediate signals
|
| 42 |
|
|
|
| 43 |
|
|
//- Instantiations ------------------------------------------------------------
|
| 44 |
|
|
|
| 45 |
|
|
sbox key_update_sbox(.data_o(s2[79:76]),.data_i(s1[79:76])); // four left-most bits are determined by the sbox output
|
| 46 |
|
|
|
| 47 |
|
|
//- Continuous Assigments------------------------------------------------------
|
| 48 |
|
|
|
| 49 |
|
|
assign s1 = {data_i[18:0],data_i[79:19]};
|
| 50 |
|
|
assign s2[75:0] = s1[75:0]; // four left-most bits are determined by the sbox output
|
| 51 |
|
|
assign s3 = {s2[79:20],(s2[19:15])^(round_counter),s2[14:0]};
|
| 52 |
|
|
assign data_o = s3;
|
| 53 |
|
|
|
| 54 |
|
|
//-----------------------------------------------------------------------------
|
| 55 |
|
|
endmodule
|
