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https://opencores.org/ocsvn/present_encryptor/present_encryptor/trunk
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rameli |
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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// Design Name: Present Cipher S-BOX //
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// Module Name: sbox //
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// Language: Verilog //
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// Date Created: 1/16/2011 //
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// Author: Reza Ameli //
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// Digital Systems Lab //
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// Ferdowsi University of Mashhad, Iran //
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// http://commeng.um.ac.ir/dslab //
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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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module sbox (data_o,data_i);
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//- Module IOs ----------------------------------------------------------------
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output reg [3:0] data_o;
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input wire [3:0] data_i;
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//- Continuous Assigments------------------------------------------------------
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always @(data_i)
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case (data_i)
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4'h0 : data_o = 4'hC;
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4'h1 : data_o = 4'h5;
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4'h2 : data_o = 4'h6;
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4'h3 : data_o = 4'hB;
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4'h4 : data_o = 4'h9;
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4'h5 : data_o = 4'h0;
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4'h6 : data_o = 4'hA;
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4'h7 : data_o = 4'hD;
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4'h8 : data_o = 4'h3;
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4'h9 : data_o = 4'hE;
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4'hA : data_o = 4'hF;
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4'hB : data_o = 4'h8;
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4'hC : data_o = 4'h4;
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4'hD : data_o = 4'h7;
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4'hE : data_o = 4'h1;
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4'hF : data_o = 4'h2;
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endcase
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//-----------------------------------------------------------------------------
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endmodule
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