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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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// Design Name: Substitution Layer for Present Cipher //
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// Module Name: substitution //
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// Language: Verilog //
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// Date Created: 1/16/2011 //
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// Author: Reza Ameli //
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// Digital Systems Lab //
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// Ferdowsi University of Mashhad, Iran //
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// http://commeng.um.ac.ir/dslab //
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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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module substitution(data_o,data_i); // Present cipher uses 16 S-Boxes in parallel to process the data
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// this module implements those 16 S-Boxes using the sbox module
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//- Module IOs ----------------------------------------------------------------
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output wire [63:0] data_o;
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input wire [63:0] data_i;
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//- Variables, Registers and Parameters ---------------------------------------
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genvar j;
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//- Instantiations ------------------------------------------------------------
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generate
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for (j = 0; j < 16; j = j+1)
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begin : boxes
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sbox substitution_sbox (.data_o(data_o[j*4+3 : j*4]),.data_i(data_i[j*4+3 : j*4]));
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end
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endgenerate
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//-----------------------------------------------------------------------------
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endmodule
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