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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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// Design Name: Test Bench for Present Encryptor Core //
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// Module Name: present_encryptor_top_tb //
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// Language: Verilog //
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// Date Created: 1/23/2011 //
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// Author: Reza Ameli //
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// Digital Systems Lab //
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// Ferdowsi University of Mashhad, Iran //
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// http://commeng.um.ac.ir/dslab //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@//
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`timescale 1ps / 1ps
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//- Test Bench ----------------------------------------------------------------
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module present_encryptor_top_tb;
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//- Variables, Registers and Parameters ---------------------------------------
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wire [63:0] data_o;
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reg [79:0] data_i;
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reg data_load;
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reg key_load;
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reg clk_i;
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//- Instantiations ------------------------------------------------------------
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present_encryptor_top UUT (.data_o(data_o),.data_i(data_i),.data_load(data_load),.key_load(key_load),.clk_i(clk_i));
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//- Behavioral Statements -----------------------------------------------------
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initial
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begin
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$monitor($realtime,,"ps %h %h %h %h %h ",data_o,data_i,data_load,key_load,clk_i);
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#0 data_i = 80'h00000000_00000000_0000 ; key_load = 1; // Key
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#10 data_i = 64'h00000000_00000000 ; key_load = 0; data_load = 1; // Plaintext
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#10 data_load = 0;
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#330 data_i = 80'hFFFFFFFF_FFFFFFFF_FFFF ; key_load = 1; // Key
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#10 data_i = 64'h00000000_00000000 ; key_load = 0; data_load = 1; // Plaintext
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#10 data_load = 0;
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#330 data_i = 80'h00000000_00000000_0000 ; key_load = 1; // Key
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#10 data_i = 64'hFFFFFFFF_FFFFFFFF ; key_load = 0; data_load = 1; // Plaintext
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#10 data_load = 0;
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#330 data_i = 80'hFFFFFFFF_FFFFFFFF_FFFF ; key_load = 1; // Key
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#10 data_i = 64'hFFFFFFFF_FFFFFFFF ; key_load = 0; data_load = 1; // Plaintext
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#10 data_load = 0;
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#330 $finish;
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end
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initial
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begin
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clk_i = 1'b0;
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forever #5 clk_i = ~clk_i;
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end
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//-----------------------------------------------------------------------------
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endmodule
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