OpenCores
URL https://opencores.org/ocsvn/product_code_iterative_decoder/product_code_iterative_decoder/trunk

Subversion Repositories product_code_iterative_decoder

[/] [product_code_iterative_decoder/] [trunk/] [bench/] [modelsim_bench.vhdl] - Blame information for rev 14

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 arif_endro
-- $Id: modelsim_bench.vhdl,v 1.1.1.1 2005-11-15 01:51:28 arif_endro Exp $
2
-------------------------------------------------------------------------------
3
-- Title       : Test bench top modules.
4
-- Project     : 
5
-------------------------------------------------------------------------------
6
-- File        : modelsim_bench.vhdl
7
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
8
-- Created     : 2005/11/01
9
-- Last update : 
10
-- Simulators  :
11
-- Synthesizers: 
12
-- Target      : 
13
-------------------------------------------------------------------------------
14
-- Description : Top modules for test bench.
15
-------------------------------------------------------------------------------
16 14 arif_endro
-- Copyright (C) 2005 Arif Endro Nugroho
17 2 arif_endro
-------------------------------------------------------------------------------
18
-- 
19
--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
20
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
21
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
22
-- ASSOCIATED DISCLAIMER.
23
-- 
24
-------------------------------------------------------------------------------
25
-- 
26
--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
29
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
32
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
34
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
35
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
-- 
37
-------------------------------------------------------------------------------
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.std_logic_arith.all;
42
use ieee.std_logic_unsigned.all;
43
 
44
entity modelsim_bench is
45
   port (
46
      y0d : out bit;
47
      y1d : out bit;
48
      y2d : out bit;
49
      y3d : out bit
50
      );
51
end modelsim_bench;
52
 
53
architecture structural of modelsim_bench is
54
 
55
   component product_code
56
      port (
57
         clock : in  bit;
58
         start : in  bit;
59
         rxin  : in  bit_vector (07 downto 00);
60
         y0d   : out bit;
61
         y1d   : out bit;
62
         y2d   : out bit;
63
         y3d   : out bit
64
         );
65
   end component;
66
 
67
   component input
68
      port (
69
         clock : out bit;
70
         start : out bit;
71
         rxin  : out bit_vector (07 downto 00)
72
         );
73
   end component;
74
 
75
   component output
76
      port (
77
         start : in bit;
78
         y0    : in bit;
79
         y1    : in bit;
80
         y2    : in bit;
81
         y3    : in bit
82
         );
83
   end component;
84
 
85
   signal clock : bit;
86
   signal start : bit;
87
   signal y0    : bit;
88
   signal y1    : bit;
89
   signal y2    : bit;
90
   signal y3    : bit;
91
   signal rxin  : bit_vector (07 downto 00);
92
 
93
   begin
94
 
95
   y0d <= y0;
96
   y1d <= y1;
97
   y2d <= y2;
98
   y3d <= y3;
99
 
100
   my_product_code : product_code
101
      port map (
102
         clock  => clock,
103
         start  => start,
104
         rxin   => rxin,
105
         y0d    => y0,
106
         y1d    => y1,
107
         y2d    => y2,
108
         y3d    => y3
109
         );
110
 
111
   my_input : input
112
      port map (
113
         clock => clock,
114
         start => start,
115
         rxin  => rxin
116
         );
117
 
118
   my_output : output
119
      port map (
120
         start => start,
121
         y0    => y0,
122
         y1    => y1,
123
         y2    => y2,
124
         y3    => y3
125
         );
126
 
127
end structural;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.