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% $Id: product_code_iterative_decoder.tex,v 1.2 2005-12-26 04:55:49 arif_endro Exp $
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% Title : Product Code Iterative Decoder
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%
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% Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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%
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% Description : Master Documentation File.
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%
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% Copyright (C) 2005 Arif E. Nugroho <arif_endro@yahoo.com>
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass[a4paper,12pt]{report}
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\usepackage[english]{babel}
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\usepackage[dvips,english,none,light,portrait]{draftcopy}
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\usepackage{fancyvrb} % enable custom verbatim env.
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\usepackage{float} % enable floating images
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\usepackage{graphicx} % enable graphics in this document
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\usepackage{titlesec} % enable customization title
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%\usepackage{times} % Default font for report
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\usepackage{indentfirst} % to make identation after sectioning
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\usepackage[pdftitle={Product Code Iterative Decoder},
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pdfauthor={Copyright (C) 2005 Arif E. Nugroho},
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pdfsubject={Product Code Decoder},
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pdfkeywords={Decoder, Turbo, Product Code},
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colorlinks=false, bookmarksnumbered=false, ps2pdf,
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]{hyperref}
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\lhead{\scriptsize{\textsf{\rightmark}}}
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\chead{}
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\lfoot{}
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\rfoot{}
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\cfoot{Arif E. Nugroho\\www.opencores.org}
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\titlelabel{\thetitle.\quad}
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{ \vspace{1pc} \LARGE\thechapter}
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{1pc} { \vspace{1pc} \Huge}
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\onehalfspacing
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% numbering in equation by chapter
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\makeatother
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\title{\\Large\textbf{Product Code Iterative Decoder}\\}
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\author{Arif E. Nugroho\\
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Department of Electrical Engineering\\
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Institut Teknologi Bandung, Indonesia\\
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e-mail: arif\_endro@yahoo.com}
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\date{}
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\begin{document}
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\begin{titlepage}
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\tt
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\thispagestyle{empty}
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\center
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{\Large\textbf{Product Code Iterative Decoder\\}}
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\vspace{2.0cm}
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\begin{figure}[H]
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\center
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\includegraphics[width=4.0cm,height=4.0cm]{oc_logo.eps}
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\end{figure}
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\vspace{1.5cm}
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\normalsize
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\textbf{Arif E. Nugroho}\\
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$\overline{\textbf{arif\_endro@opencores.org}}$
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\vspace{1.50cm}
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\begin{figure}[H]
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\center
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\includegraphics[width=4.0cm,height=4.0cm]{logo.eps}
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\end{figure}
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\vspace{1.50cm}
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\textbf{
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\begin{tabular}{p{2.0cm}p{12cm}}
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& VLSI Research Group\\
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& LabTek VIII Institut Teknologi Bandung\\
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& Jl.~Ganesha 10 Bandung 40141\\
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& West Java, Indonesia\\
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\end{tabular}
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}
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\end{titlepage}
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\pagenumbering{roman}
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\tableofcontents
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\listoffigures
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\pagestyle{fancy}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\vspace{2cm}
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\section{Product Code}
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Product code is also known as turbo code, this error correction methods
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is known to approach the Shannon Limit. This design uses iterative
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methods on decoding the product codes, see Figure~\ref{schematics}, this
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design is based on Mr.~Wada-san homepage\cite{wada}.
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This is two dimesional product code iterative decoder, there are four
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bits information followed by two row parity bits and two column parity
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bits. Each signal informations is represented in two's complement eight
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bit data, thus it indicate an integer value of -128 to 127 for each of
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information bit.
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\vspace{1cm}
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\begin{figure}[H]
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\center
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\includegraphics[width=9cm,height=2cm]{sequence.eps}
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\caption{Sequence of Product Codes}
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\label{sequence}
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\end{figure}
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\begin{figure}[H]
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\center
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\includegraphics[width=8cm,height=4cm]{product_codes_table.eps}
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\caption{Product Code generations}
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\label{product_code}
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\end{figure}
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\section{Decoding Algorithm}
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\begin{equation}
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posteriori~value = channel~value~(Lch) + priori~value +
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external~value~(Le)
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\end{equation}
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\begin{equation}
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\left\{
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\begin{array}{lr}
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posteriori = Lch~+~priori~+~Le~(row~parity) & (0)\\
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posteriori = Lch~+~priori~+~Le~(column~parity) & (1)\\
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....\\
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....\\
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posteriori = Lch~+~priori~+~Le~(row~parity) & (n-1)\\
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posteriori = Lch~+~priori~+~Le~(column~parity) & (n)\\
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\end{array}
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\right\}
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\end{equation}
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\begin{equation}
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Lch = Y0,~Y1,~Y2,~Y3
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\end{equation}
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\begin{equation}
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priori = posteriori~(n-1)
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\end{equation}
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\begin{equation}
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Le = sgn(a~*~b)~*~min\{abs(a),abs(b)\}
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\end{equation}
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sgn(a~*~b) means the sign result of multiplication between operand a and
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b, and abs(x) means absolute value of operand x. The last value of
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posteriori is the decoded informations, i.e the posteriori value at
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n$^{th}$ iterations. The decoded informations can be obtained from the
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sign of the last posteriori value, positive value is zero and negative
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value is one, i.e this is the most significant bit of the posteriori
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value.
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\section{Circuit Schematic}
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\begin{figure}[H]
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\center
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\includegraphics[width=15cm,height=9.0cm]{schematic.eps}
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\caption{Schematic of Product Code Decoder}
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\label{schematics}
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\end{figure}
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\chapter{Implementation}
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\vspace{2cm}
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\section{Simulation}
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\begin{figure}[H]
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\center
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\includegraphics[width=12cm,height=6cm]{screenshot.eps}
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\caption{Simulation waveform}
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\label{simulation waveform}
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\end{figure}
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This design has been simulated using ModelSim 6.0 SE, here is the
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summary of bit errors on different signal to noise ratio (SNR) of input
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signal:
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\begin{table}[H]
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\center
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\includegraphics[width=8cm,height=2.5cm]{bit_errors.eps}
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\caption{Bit errors on different SNR}
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\label{bit_errors}
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\end{table}
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signal with SNR 0 dB is signal with very big noise.
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\section{Synthesize}
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This design has been synthesized using ISE Xilinx 6.3i, here is the
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summary of the area utilization in FPGA Xilinx:
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\begin{table}[H]
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\center
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\includegraphics[width=8cm,height=2.5cm]{area.eps}
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\caption{Area utilizations summary}
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\label{area}
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\end{table}
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The maximum clock frequency is 64.045 MHz (Minimum period 15.614ns)
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\begin{thebibliography}{1}
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\bibitem{wada}
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Tom Wada, \textbf{2-D Product Code Iterative Decoder},\\
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\href{http://www.ie.u-ryukyu.ac.jp/\~\ wada/design06/spec\_e.html}
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{http://www.ie.u-ryukyu.ac.jp/\~\ wada/design06/spec\_e.html}\\
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October 1$^{st}$, 2005
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\end{thebibliography}
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\appendix
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\chapter{Informations}
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\section{Warranty}
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\begin{center}
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\textbf{\texttt{NO WARRANTY}}\\
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\end{center}
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\textbf{\scriptsize{
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THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.}}
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\section{Tools}
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\begin{itemize}
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\item ALLIANCE CAD SYSTEM developed by ASIM
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team at \copyright LIP6/Universit\'{e} Pierre et
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Marie Curie,
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\href{http://asim.lip6.fr/recherche/alliance}{\textbf{http://asim.lip6.fr/recherche/alliance}}\\
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The primary VHDL Analyser for Synthesize
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\item \textbf{ModelSim 6.0} The Simulator
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\item \textbf{Xilinx 6.3i} The Synthesizer
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\item \textbf{VIM} (Vi IMproved) The Editor
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\item \textbf{\LaTeX}~~The Typesetter
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\end{itemize}
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\vspace{15cm}
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\begin{tabbing}
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\textbf{Version: 1.0}
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\end{tabbing}
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\end{document}
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