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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_wb_if.v                                                 ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/02/20 16:35:43  mihad
// Little/big endian changes continued
//
// Revision 1.3  2002/02/20 15:20:10  mihad
// Little/big endian changes incorporated
//
// Revision 1.2  2002/02/18 18:07:55  mihad
// One bug fixed
//
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
// Initial project import - working
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_wb_if
(
    wb_clk_i,
    wb_rst_i,
    wb_cyc_i,
    wb_stb_i,
    wb_we_i,
    wb_sel_i,
    wb_adr_i,
    wb_dat_i,
    wb_dat_o,
    wb_ack_o,
 
    wb_int_o,
 
    tx_kbd_write_ack_i,
    tx_kbd_data_o,
    tx_kbd_write_o,
    rx_scancode_i,
    rx_kbd_data_ready_i,
    rx_kbd_read_o,
    translate_o,
    ps2_kbd_clk_i,
    inhibit_kbd_if_o
    `ifdef PS2_AUX
    ,
    wb_intb_o,
 
    rx_aux_data_i,
    rx_aux_data_ready_i,
    rx_aux_read_o,
    tx_aux_data_o,
    tx_aux_write_o,
    tx_aux_write_ack_i,
    ps2_aux_clk_i,
    inhibit_aux_if_o
`endif
) ;
 
input wb_clk_i,
      wb_rst_i,
      wb_cyc_i,
      wb_stb_i,
      wb_we_i ;
 
input [3:0]  wb_sel_i ;
 
input [31:0] wb_adr_i ;
 
input [31:0]  wb_dat_i ;
 
output [31:0] wb_dat_o ;
 
output wb_ack_o ;
 
reg wb_ack_o ;
 
output wb_int_o ;
reg    wb_int_o ;
 
input tx_kbd_write_ack_i ;
 
input [7:0] rx_scancode_i ;
input       rx_kbd_data_ready_i ;
output      rx_kbd_read_o ;
 
output      tx_kbd_write_o ;
output [7:0] tx_kbd_data_o ;
 
output translate_o ;
input  ps2_kbd_clk_i ;
 
output inhibit_kbd_if_o ;
 
reg [7:0] input_buffer,
          output_buffer ;
 
reg [7:0] wb_dat_i_sampled ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_i_sampled <= #1 0 ;
    else if ( wb_cyc_i && wb_stb_i && wb_we_i )
        wb_dat_i_sampled <= #1 wb_dat_i[31:24] ;
end
 
`ifdef PS2_AUX
output wb_intb_o ;
reg    wb_intb_o ;
 
input  [7:0]    rx_aux_data_i ;
input           rx_aux_data_ready_i ;
output          rx_aux_read_o ;
output [7:0]    tx_aux_data_o ;
output          tx_aux_write_o ;
input           tx_aux_write_ack_i ;
input           ps2_aux_clk_i ;
output          inhibit_aux_if_o ;
reg             inhibit_aux_if_o ;
reg             aux_output_buffer_full ;
reg             aux_input_buffer_full ;
reg             interrupt2 ;
reg             enable2    ;
assign          tx_aux_data_o  = output_buffer ;
assign          tx_aux_write_o = aux_output_buffer_full ;
`else
wire aux_input_buffer_full  = 1'b0 ;
wire aux_output_buffer_full = 1'b0 ;
wire interrupt2             = 1'b0 ;
wire enable2                = 1'b1 ;
`endif
 
assign tx_kbd_data_o = output_buffer ;
 
reg input_buffer_full,   // receive buffer
    output_buffer_full ; // transmit buffer
 
assign tx_kbd_write_o = output_buffer_full ;
 
wire system_flag ;
wire a2                       = 1'b0 ;
wire kbd_inhibit              = ps2_kbd_clk_i ;
wire timeout                  = 1'b0 ;
wire perr                     = 1'b0 ;
 
wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full || aux_output_buffer_full, input_buffer_full} ;
 
reg  read_input_buffer_reg ;
wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
 
reg  write_output_buffer_reg ;
wire write_output_buffer  = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i  && (wb_adr_i[2:0] == 3'h0) ;
 
reg  read_status_register_reg ;
wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
 
reg  send_command_reg ;
wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i  && (wb_adr_i[2:0] == 3'h4) ;
 
reg  translate_o,
     enable1,
     system,
     interrupt1 ;
 
reg inhibit_kbd_if_o ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        inhibit_kbd_if_o <= #1 1'b1 ;
    else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)
        inhibit_kbd_if_o <= #1 1'b1 ;
    else if ( !rx_kbd_data_ready_i || enable1 )
        inhibit_kbd_if_o <= #1 1'b0 ;
 
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        inhibit_aux_if_o <= #1 1'b1 ;
    else if ( ps2_aux_clk_i && rx_aux_data_ready_i && !enable2 )
        inhibit_aux_if_o <= #1 1'b1 ;
    else if ( !rx_aux_data_ready_i || enable2 )
        inhibit_aux_if_o <= #1 1'b0 ;
 
end
`endif
 
assign system_flag = system ;
 
wire [7:0] command_byte = {1'b0, translate_o, enable2, enable1, 1'b0, system, interrupt2, interrupt1} ;
 
reg [7:0] current_command ;
reg [7:0] current_command_output ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        send_command_reg         <= #1 1'b0 ;
        read_input_buffer_reg    <= #1 1'b0 ;
        write_output_buffer_reg  <= #1 1'b0 ;
        read_status_register_reg <= #1 1'b0 ;
    end
    else
    begin
        send_command_reg         <= #1 send_command ;
        read_input_buffer_reg    <= #1 read_input_buffer ;
        write_output_buffer_reg  <= #1 write_output_buffer ;
        read_status_register_reg <= #1 read_status_register ;
    end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        current_command <= #1 8'h0 ;
    else if ( send_command_reg )
        current_command <= #1 wb_dat_i_sampled ;
end
 
reg current_command_valid,
    current_command_returns_value,
    current_command_gets_parameter,
    current_command_gets_null_terminated_string ;
 
reg write_output_buffer_reg_previous ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        write_output_buffer_reg_previous <= #1 1'b0 ;
    else
        write_output_buffer_reg_previous <= #1 write_output_buffer_reg ;
end
 
wire invalidate_current_command =
     current_command_valid &&
     (( current_command_returns_value && read_input_buffer_reg && input_buffer_full) ||
      ( current_command_gets_parameter && write_output_buffer_reg_previous ) ||
      ( current_command_gets_null_terminated_string && write_output_buffer_reg_previous && (output_buffer == 8'h00) ) ||
      ( !current_command_returns_value && !current_command_gets_parameter && !current_command_gets_null_terminated_string )
     ) ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        current_command_valid <= #1 1'b0 ;
    else if ( invalidate_current_command )
        current_command_valid <= #1 1'b0 ;
    else if ( send_command_reg )
        current_command_valid <= #1 1'b1 ;
 
end
 
reg write_command_byte ;
reg current_command_output_valid ;
always@(
    current_command or
    command_byte or
    write_output_buffer_reg_previous or
    current_command_valid or
    output_buffer
)
begin
    current_command_returns_value               = 1'b0 ;
    current_command_gets_parameter              = 1'b0 ;
    current_command_gets_null_terminated_string = 1'b0 ;
    current_command_output                      = 8'h00 ;
    write_command_byte                          = 1'b0 ;
    current_command_output_valid                = 1'b0 ;
    case(current_command)
        8'h20:begin
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = command_byte ;
                  current_command_output_valid   = 1'b1 ;
              end
        8'h60:begin
                  current_command_gets_parameter = 1'b1 ;
                  write_command_byte             = write_output_buffer_reg_previous && current_command_valid ;
              end
        8'hA1:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hA4:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hF1 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hA5:begin
                  current_command_gets_null_terminated_string = 1'b1 ;
              end
        8'hA6:begin
              end
        8'hA7:begin
              end
        8'hA8:begin
              end
        8'hA9:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output_valid  = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_output        = 8'h00 ;  // interface OK
                  `else
                  current_command_output        = 8'h02 ; // clock line stuck high
                  `endif
              end
        8'hAA:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h55 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAB:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAD:begin
              end
        8'hAE:begin
              end
        8'hAF:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC1:begin
              end
        8'hC2:begin
              end
        8'hD0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h01 ; // only system reset bit is 1
                  current_command_output_valid  = 1'b1 ;
              end
        8'hD1:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hD2:begin
                  current_command_returns_value   = 1'b1 ;
                  current_command_gets_parameter  = 1'b1 ;
                  current_command_output          = output_buffer ;
                  current_command_output_valid    = write_output_buffer_reg_previous ;
              end
        8'hD3:begin
                  current_command_gets_parameter = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = output_buffer ;
                  current_command_output_valid   = write_output_buffer_reg_previous ;
                  `endif
              end
        8'hD4:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hE0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
    endcase
end
 
reg cyc_i_previous ;
reg stb_i_previous ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else if ( wb_ack_o )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else
    begin
        cyc_i_previous <= #1 wb_cyc_i ;
        stb_i_previous <= #1 wb_stb_i ;
    end
 
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_ack_o <= #1 1'b0 ;
    else if ( wb_ack_o )
        wb_ack_o <= #1 1'b0 ;
    else
        wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;
end
 
reg [31:0] wb_dat_o ;
wire wb_read = read_input_buffer_reg || read_status_register_reg ;
 
wire [7:0] output_data = read_status_register_reg ? status_byte : input_buffer ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_o <= #1 32'h0 ;
    else if ( wb_read )
        wb_dat_o <= #1 {4{output_data}} ;
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer_full <= #1 1'b0 ;
    else if ( output_buffer_full && tx_kbd_write_ack_i || enable1)
        output_buffer_full <= #1 1'b0 ;
    else
        output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid || (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_output_buffer_full <= #1 1'b0 ;
    else if ( aux_output_buffer_full && tx_aux_write_ack_i || enable2)
        aux_output_buffer_full <= #1 1'b0 ;
    else
        aux_output_buffer_full <= #1 write_output_buffer_reg && current_command_valid && (current_command == 8'hD4) ;
end
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer <= #1 8'h00 ;
    else if ( write_output_buffer_reg )
        output_buffer <= #1 wb_dat_i_sampled ;
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        translate_o <= #1 1'b0 ;
        system      <= #1 1'b0 ;
        interrupt1  <= #1 1'b0 ;
        `ifdef PS2_AUX
        interrupt2  <= #1 1'b0 ;
        `endif
    end
    else if ( write_command_byte )
    begin
        translate_o <= #1 output_buffer[6] ;
        system      <= #1 output_buffer[2] ;
        interrupt1  <= #1 output_buffer[0] ;
        `ifdef PS2_AUX
        interrupt2  <= #1 output_buffer[1] ;
        `endif
    end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable1 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hAE) )
        enable1 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hAD) )
        enable1 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable1 <= #1 output_buffer[4] ;
 
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable2 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hA8) )
        enable2 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hA7) )
        enable2 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable2 <= #1 output_buffer[5] ;
 
end
`endif
 
wire write_input_buffer_from_command = current_command_valid && current_command_returns_value && current_command_output_valid ;
wire write_input_buffer_from_kbd     = !input_buffer_full && rx_kbd_data_ready_i && !enable1 && !current_command_valid ;
 
`ifdef PS2_AUX
wire write_input_buffer_from_aux     = !input_buffer_full && rx_aux_data_ready_i && !enable2 && !current_command_valid && !write_input_buffer_from_kbd ;
`endif
 
wire load_input_buffer_value =
    write_input_buffer_from_command
    ||
    write_input_buffer_from_kbd
    `ifdef PS2_AUX
    ||
    write_input_buffer_from_aux
    `endif
    ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_full <= #1 1'b0 ;
    else if ( load_input_buffer_value )
        input_buffer_full <= #1 1'b1 ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( write_input_buffer_from_aux || (write_input_buffer_from_command && (current_command == 8'hD3)) )
        aux_input_buffer_full <= #1 1'b1 ;
end
`endif
 
reg input_buffer_filled_from_command ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( write_input_buffer_from_command )
        input_buffer_filled_from_command <= #1 1'b1 ;
end
 
`ifdef PS2_AUX
reg [7:0] value_to_load_in_input_buffer ;
always@
(
    write_input_buffer_from_command
    or
    current_command_output
    or
    rx_scancode_i
    or
    write_input_buffer_from_kbd
    or
    rx_aux_data_i
)
begin
    case ({write_input_buffer_from_command, write_input_buffer_from_kbd})
        2'b10,
        2'b11   :   value_to_load_in_input_buffer = current_command_output ;
        2'b01   :   value_to_load_in_input_buffer = rx_scancode_i ;
        2'b00   :   value_to_load_in_input_buffer = rx_aux_data_i ;
    endcase
end
 
`else
wire [7:0] value_to_load_in_input_buffer = write_input_buffer_from_command ? current_command_output : rx_scancode_i ;
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer <= #1 8'h00 ;
    else if ( load_input_buffer_value )
        input_buffer <= #1 value_to_load_in_input_buffer ;
end
 
assign rx_kbd_read_o = rx_kbd_data_ready_i &&
                       ( enable1
                         ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                           `ifdef PS2_AUX
                           &&
                           !aux_input_buffer_full
                           `endif
                          )
                        );
 
`ifdef PS2_AUX
assign rx_aux_read_o = rx_aux_data_ready_i &&
                       ( enable2 ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           aux_input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                          )
                        );
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_int_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable1 || !interrupt1)
        wb_int_o <= #1 1'b0 ;
    else
        wb_int_o <= #1 input_buffer_full
                       `ifdef PS2_AUX
                       &&
                       !aux_input_buffer_full
                       `endif
                       ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_intb_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable2 || !interrupt2)
        wb_intb_o <= #1 1'b0 ;
    else
        wb_intb_o <= #1 input_buffer_full
                       &&
                       aux_input_buffer_full
                       ;
end
`endif
 
endmodule // ps2_wb_if

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_wb_if.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	13	mihad	`// Revision 1.4 2002/02/20 16:35:43 mihad`
47			`// Little/big endian changes continued`
48			`//`
49	7	mihad	`// Revision 1.3 2002/02/20 15:20:10 mihad`
50			`// Little/big endian changes incorporated`
51			`//`
52	6	mihad	`// Revision 1.2 2002/02/18 18:07:55 mihad`
53			`// One bug fixed`
54			`//`
55	5	mihad	`// Revision 1.1.1.1 2002/02/18 16:16:56 mihad`
56			`// Initial project import - working`
57	2	mihad	`//`
58	5	mihad	`//`
59	2	mihad
60			`// synopsys translate_off`
61			`include "timescale.v"
62			`// synopsys translate_on`
63
64			`module ps2_wb_if`
65			`(`
66			`wb_clk_i,`
67			`wb_rst_i,`
68			`wb_cyc_i,`
69			`wb_stb_i,`
70			`wb_we_i,`
71			`wb_sel_i,`
72			`wb_adr_i,`
73			`wb_dat_i,`
74			`wb_dat_o,`
75			`wb_ack_o,`
76	13	mihad
77	2	mihad	`wb_int_o,`
78
79	13	mihad	`tx_kbd_write_ack_i,`
80			`tx_kbd_data_o,`
81			`tx_kbd_write_o,`
82	2	mihad	`rx_scancode_i,`
83	13	mihad	`rx_kbd_data_ready_i,`
84			`rx_kbd_read_o,`
85	2	mihad	`translate_o,`
86	13	mihad	`ps2_kbd_clk_i,`
87	2	mihad	`inhibit_kbd_if_o`
88	13	mihad	`ifdef PS2_AUX
89			`,`
90			`wb_intb_o,`
91
92			`rx_aux_data_i,`
93			`rx_aux_data_ready_i,`
94			`rx_aux_read_o,`
95			`tx_aux_data_o,`
96			`tx_aux_write_o,`
97			`tx_aux_write_ack_i,`
98			`ps2_aux_clk_i,`
99			`inhibit_aux_if_o`
100			`endif
101	2	mihad	`) ;`
102
103			`input wb_clk_i,`
104			`wb_rst_i,`
105			`wb_cyc_i,`
106			`wb_stb_i,`
107			`wb_we_i ;`
108
109			`input [3:0] wb_sel_i ;`
110
111			`input [31:0] wb_adr_i ;`
112
113			`input [31:0] wb_dat_i ;`
114
115			`output [31:0] wb_dat_o ;`
116
117			`output wb_ack_o ;`
118
119			`reg wb_ack_o ;`
120
121			`output wb_int_o ;`
122			`reg wb_int_o ;`
123
124	13	mihad	`input tx_kbd_write_ack_i ;`
125	2	mihad
126			`input [7:0] rx_scancode_i ;`
127	13	mihad	`input rx_kbd_data_ready_i ;`
128			`output rx_kbd_read_o ;`
129	2	mihad
130	13	mihad	`output tx_kbd_write_o ;`
131			`output [7:0] tx_kbd_data_o ;`
132	2	mihad
133			`output translate_o ;`
134	13	mihad	`input ps2_kbd_clk_i ;`
135	2	mihad
136			`output inhibit_kbd_if_o ;`
137
138			`reg [7:0] input_buffer,`
139			`output_buffer ;`
140
141	13	mihad	`reg [7:0] wb_dat_i_sampled ;`
142			`always@(posedge wb_clk_i or posedge wb_rst_i)`
143			`begin`
144			`if ( wb_rst_i )`
145			`wb_dat_i_sampled <= #1 0 ;`
146			`else if ( wb_cyc_i && wb_stb_i && wb_we_i )`
147			`wb_dat_i_sampled <= #1 wb_dat_i[31:24] ;`
148			`end`
149	2	mihad
150	13	mihad	`ifdef PS2_AUX
151			`output wb_intb_o ;`
152			`reg wb_intb_o ;`
153
154			`input [7:0] rx_aux_data_i ;`
155			`input rx_aux_data_ready_i ;`
156			`output rx_aux_read_o ;`
157			`output [7:0] tx_aux_data_o ;`
158			`output tx_aux_write_o ;`
159			`input tx_aux_write_ack_i ;`
160			`input ps2_aux_clk_i ;`
161			`output inhibit_aux_if_o ;`
162			`reg inhibit_aux_if_o ;`
163			`reg aux_output_buffer_full ;`
164			`reg aux_input_buffer_full ;`
165			`reg interrupt2 ;`
166			`reg enable2 ;`
167			`assign tx_aux_data_o = output_buffer ;`
168			`assign tx_aux_write_o = aux_output_buffer_full ;`
169			`else
170			`wire aux_input_buffer_full = 1'b0 ;`
171			`wire aux_output_buffer_full = 1'b0 ;`
172			`wire interrupt2 = 1'b0 ;`
173			`wire enable2 = 1'b1 ;`
174			`endif
175
176			`assign tx_kbd_data_o = output_buffer ;`
177
178	2	mihad	`reg input_buffer_full, // receive buffer`
179			`output_buffer_full ; // transmit buffer`
180
181	13	mihad	`assign tx_kbd_write_o = output_buffer_full ;`
182	2	mihad
183			`wire system_flag ;`
184			`wire a2 = 1'b0 ;`
185	13	mihad	`wire kbd_inhibit = ps2_kbd_clk_i ;`
186	2	mihad	`wire timeout = 1'b0 ;`
187			`wire perr = 1'b0 ;`
188
189	13	mihad	`wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full \|\| aux_output_buffer_full, input_buffer_full} ;`
190	2	mihad
191			`reg read_input_buffer_reg ;`
192	6	mihad	`wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;`
193	2	mihad
194			`reg write_output_buffer_reg ;`
195	6	mihad	`wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[2:0] == 3'h0) ;`
196	2	mihad
197			`reg read_status_register_reg ;`
198	6	mihad	`wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;`
199	2	mihad
200			`reg send_command_reg ;`
201	6	mihad	`wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[2:0] == 3'h4) ;`
202	2	mihad
203			`reg translate_o,`
204			`enable1,`
205			`system,`
206			`interrupt1 ;`
207
208			`reg inhibit_kbd_if_o ;`
209			`always@(posedge wb_clk_i or posedge wb_rst_i)`
210			`begin`
211			`if ( wb_rst_i )`
212			`inhibit_kbd_if_o <= #1 1'b1 ;`
213	13	mihad	`else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)`
214	2	mihad	`inhibit_kbd_if_o <= #1 1'b1 ;`
215	13	mihad	`else if ( !rx_kbd_data_ready_i \|\| enable1 )`
216	2	mihad	`inhibit_kbd_if_o <= #1 1'b0 ;`
217	13	mihad
218	2	mihad	`end`
219
220	13	mihad	`ifdef PS2_AUX
221			`always@(posedge wb_clk_i or posedge wb_rst_i)`
222			`begin`
223			`if ( wb_rst_i )`
224			`inhibit_aux_if_o <= #1 1'b1 ;`
225			`else if ( ps2_aux_clk_i && rx_aux_data_ready_i && !enable2 )`
226			`inhibit_aux_if_o <= #1 1'b1 ;`
227			`else if ( !rx_aux_data_ready_i \|\| enable2 )`
228			`inhibit_aux_if_o <= #1 1'b0 ;`
229	2	mihad
230	13	mihad	`end`
231			`endif
232
233	2	mihad	`assign system_flag = system ;`
234
235			`wire [7:0] command_byte = {1'b0, translate_o, enable2, enable1, 1'b0, system, interrupt2, interrupt1} ;`
236
237			`reg [7:0] current_command ;`
238			`reg [7:0] current_command_output ;`
239
240			`always@(posedge wb_clk_i or posedge wb_rst_i)`
241			`begin`
242			`if ( wb_rst_i )`
243			`begin`
244			`send_command_reg <= #1 1'b0 ;`
245			`read_input_buffer_reg <= #1 1'b0 ;`
246			`write_output_buffer_reg <= #1 1'b0 ;`
247			`read_status_register_reg <= #1 1'b0 ;`
248			`end`
249			`else`
250			`begin`
251			`send_command_reg <= #1 send_command ;`
252			`read_input_buffer_reg <= #1 read_input_buffer ;`
253			`write_output_buffer_reg <= #1 write_output_buffer ;`
254			`read_status_register_reg <= #1 read_status_register ;`
255			`end`
256			`end`
257
258			`always@(posedge wb_clk_i or posedge wb_rst_i)`
259			`begin`
260			`if ( wb_rst_i )`
261			`current_command <= #1 8'h0 ;`
262			`else if ( send_command_reg )`
263	13	mihad	`current_command <= #1 wb_dat_i_sampled ;`
264	2	mihad	`end`
265
266			`reg current_command_valid,`
267			`current_command_returns_value,`
268			`current_command_gets_parameter,`
269			`current_command_gets_null_terminated_string ;`
270
271			`reg write_output_buffer_reg_previous ;`
272			`always@(posedge wb_clk_i or posedge wb_rst_i)`
273			`begin`
274			`if ( wb_rst_i )`
275			`write_output_buffer_reg_previous <= #1 1'b0 ;`
276			`else`
277			`write_output_buffer_reg_previous <= #1 write_output_buffer_reg ;`
278			`end`
279
280	13	mihad	`wire invalidate_current_command =`
281			`current_command_valid &&`
282	2	mihad	`(( current_command_returns_value && read_input_buffer_reg && input_buffer_full) \|\|`
283			`( current_command_gets_parameter && write_output_buffer_reg_previous ) \|\|`
284			`( current_command_gets_null_terminated_string && write_output_buffer_reg_previous && (output_buffer == 8'h00) ) \|\|`
285			`( !current_command_returns_value && !current_command_gets_parameter && !current_command_gets_null_terminated_string )`
286			`) ;`
287
288			`always@(posedge wb_clk_i or posedge wb_rst_i)`
289			`begin`
290			`if ( wb_rst_i )`
291			`current_command_valid <= #1 1'b0 ;`
292			`else if ( invalidate_current_command )`
293			`current_command_valid <= #1 1'b0 ;`
294			`else if ( send_command_reg )`
295			`current_command_valid <= #1 1'b1 ;`
296	13	mihad
297	2	mihad	`end`
298
299			`reg write_command_byte ;`
300			`reg current_command_output_valid ;`
301			`always@(`
302			`current_command or`
303			`command_byte or`
304	13	mihad	`write_output_buffer_reg_previous or`
305	2	mihad	`current_command_valid or`
306			`output_buffer`
307			`)`
308			`begin`
309			`current_command_returns_value = 1'b0 ;`
310			`current_command_gets_parameter = 1'b0 ;`
311			`current_command_gets_null_terminated_string = 1'b0 ;`
312			`current_command_output = 8'h00 ;`
313			`write_command_byte = 1'b0 ;`
314			`current_command_output_valid = 1'b0 ;`
315			`case(current_command)`
316			`8'h20:begin`
317			`current_command_returns_value = 1'b1 ;`
318			`current_command_output = command_byte ;`
319			`current_command_output_valid = 1'b1 ;`
320			`end`
321			`8'h60:begin`
322			`current_command_gets_parameter = 1'b1 ;`
323			`write_command_byte = write_output_buffer_reg_previous && current_command_valid ;`
324			`end`
325			`8'hA1:begin`
326			`current_command_returns_value = 1'b1 ;`
327			`current_command_output = 8'h00 ;`
328			`current_command_output_valid = 1'b1 ;`
329	13	mihad	`end`
330	2	mihad	`8'hA4:begin`
331			`current_command_returns_value = 1'b1 ;`
332			`current_command_output = 8'hF1 ;`
333			`current_command_output_valid = 1'b1 ;`
334			`end`
335			`8'hA5:begin`
336			`current_command_gets_null_terminated_string = 1'b1 ;`
337			`end`
338			`8'hA6:begin`
339			`end`
340			`8'hA7:begin`
341	13	mihad	`end`
342	2	mihad	`8'hA8:begin`
343			`end`
344			`8'hA9:begin`
345			`current_command_returns_value = 1'b1 ;`
346	13	mihad	`current_command_output_valid = 1'b1 ;`
347			`ifdef PS2_AUX
348			`current_command_output = 8'h00 ; // interface OK`
349			`else
350	2	mihad	`current_command_output = 8'h02 ; // clock line stuck high`
351	13	mihad	`endif
352	2	mihad	`end`
353			`8'hAA:begin`
354			`current_command_returns_value = 1'b1 ;`
355			`current_command_output = 8'h55 ;`
356			`current_command_output_valid = 1'b1 ;`
357			`end`
358			`8'hAB:begin`
359			`current_command_returns_value = 1'b1 ;`
360			`current_command_output = 8'h00 ;`
361			`current_command_output_valid = 1'b1 ;`
362			`end`
363			`8'hAD:begin`
364	13	mihad	`end`
365	2	mihad	`8'hAE:begin`
366			`end`
367			`8'hAF:begin`
368			`current_command_returns_value = 1'b1 ;`
369			`current_command_output = 8'h00 ;`
370			`current_command_output_valid = 1'b1 ;`
371			`end`
372	13	mihad	`8'hC0:begin`
373	2	mihad	`current_command_returns_value = 1'b1 ;`
374			`current_command_output = 8'hFF ;`
375			`current_command_output_valid = 1'b1 ;`
376			`end`
377			`8'hC1:begin`
378			`end`
379			`8'hC2:begin`
380			`end`
381			`8'hD0:begin`
382			`current_command_returns_value = 1'b1 ;`
383			`current_command_output = 8'h01 ; // only system reset bit is 1`
384			`current_command_output_valid = 1'b1 ;`
385			`end`
386			`8'hD1:begin`
387			`current_command_gets_parameter = 1'b1 ;`
388			`end`
389			`8'hD2:begin`
390	5	mihad	`current_command_returns_value = 1'b1 ;`
391	2	mihad	`current_command_gets_parameter = 1'b1 ;`
392			`current_command_output = output_buffer ;`
393			`current_command_output_valid = write_output_buffer_reg_previous ;`
394			`end`
395			`8'hD3:begin`
396			`current_command_gets_parameter = 1'b1 ;`
397	13	mihad	`ifdef PS2_AUX
398			`current_command_returns_value = 1'b1 ;`
399			`current_command_output = output_buffer ;`
400			`current_command_output_valid = write_output_buffer_reg_previous ;`
401			`endif
402	2	mihad	`end`
403			`8'hD4:begin`
404			`current_command_gets_parameter = 1'b1 ;`
405			`end`
406			`8'hE0:begin`
407			`current_command_returns_value = 1'b1 ;`
408			`current_command_output = 8'hFF ;`
409			`current_command_output_valid = 1'b1 ;`
410			`end`
411	13	mihad	`endcase`
412	2	mihad	`end`
413
414			`reg cyc_i_previous ;`
415			`reg stb_i_previous ;`
416
417			`always@(posedge wb_clk_i or posedge wb_rst_i)`
418			`begin`
419			`if ( wb_rst_i )`
420			`begin`
421			`cyc_i_previous <= #1 1'b0 ;`
422			`stb_i_previous <= #1 1'b0 ;`
423			`end`
424			`else if ( wb_ack_o )`
425			`begin`
426			`cyc_i_previous <= #1 1'b0 ;`
427			`stb_i_previous <= #1 1'b0 ;`
428			`end`
429			`else`
430			`begin`
431			`cyc_i_previous <= #1 wb_cyc_i ;`
432			`stb_i_previous <= #1 wb_stb_i ;`
433			`end`
434	13	mihad
435	2	mihad	`end`
436
437			`always@(posedge wb_clk_i or posedge wb_rst_i)`
438			`begin`
439			`if ( wb_rst_i )`
440			`wb_ack_o <= #1 1'b0 ;`
441			`else if ( wb_ack_o )`
442			`wb_ack_o <= #1 1'b0 ;`
443			`else`
444			`wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;`
445			`end`
446
447			`reg [31:0] wb_dat_o ;`
448			`wire wb_read = read_input_buffer_reg \|\| read_status_register_reg ;`
449
450			`wire [7:0] output_data = read_status_register_reg ? status_byte : input_buffer ;`
451			`always@(posedge wb_clk_i or posedge wb_rst_i)`
452			`begin`
453			`if ( wb_rst_i )`
454			`wb_dat_o <= #1 32'h0 ;`
455			`else if ( wb_read )`
456			`wb_dat_o <= #1 {4{output_data}} ;`
457			`end`
458
459			`always@(posedge wb_clk_i or posedge wb_rst_i)`
460			`begin`
461			`if ( wb_rst_i )`
462			`output_buffer_full <= #1 1'b0 ;`
463	13	mihad	`else if ( output_buffer_full && tx_kbd_write_ack_i \|\| enable1)`
464			`output_buffer_full <= #1 1'b0 ;`
465			`else`
466	2	mihad	`output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid \|\| (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;`
467			`end`
468
469	13	mihad	`ifdef PS2_AUX
470	2	mihad	`always@(posedge wb_clk_i or posedge wb_rst_i)`
471			`begin`
472			`if ( wb_rst_i )`
473	13	mihad	`aux_output_buffer_full <= #1 1'b0 ;`
474			`else if ( aux_output_buffer_full && tx_aux_write_ack_i \|\| enable2)`
475			`aux_output_buffer_full <= #1 1'b0 ;`
476			`else`
477			`aux_output_buffer_full <= #1 write_output_buffer_reg && current_command_valid && (current_command == 8'hD4) ;`
478			`end`
479			`endif
480
481			`always@(posedge wb_clk_i or posedge wb_rst_i)`
482			`begin`
483			`if ( wb_rst_i )`
484	2	mihad	`output_buffer <= #1 8'h00 ;`
485			`else if ( write_output_buffer_reg )`
486	13	mihad	`output_buffer <= #1 wb_dat_i_sampled ;`
487	2	mihad	`end`
488
489			`always@(posedge wb_clk_i or posedge wb_rst_i)`
490			`begin`
491			`if ( wb_rst_i )`
492			`begin`
493			`translate_o <= #1 1'b0 ;`
494			`system <= #1 1'b0 ;`
495			`interrupt1 <= #1 1'b0 ;`
496	13	mihad	`ifdef PS2_AUX
497			`interrupt2 <= #1 1'b0 ;`
498			`endif
499	2	mihad	`end`
500			`else if ( write_command_byte )`

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