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[/] [ps2/] [tags/] [rel_10/] [bench/] [verilog/] [ps2_sim_top.v] - Blame information for rev 23

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1 2 mihad
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  ps2_sim_top.v                                               ////
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////                                                              ////
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////  This file is part of the "ps2" project                      ////
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////  http://www.opencores.org/cores/ps2/                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - mihad@opencores.org                                   ////
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////      - Miha Dolenc                                           ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
46 23 mihad
// Revision 1.3  2003/05/28 16:26:51  simons
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// Change the address width.
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//
49 15 simons
// Revision 1.2  2002/04/09 13:16:04  mihad
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// Mouse interface added
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//
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// Revision 1.1.1.1  2002/02/18 16:16:55  mihad
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// Initial project import - working
54 2 mihad
//
55 11 mihad
//
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57 11 mihad
`include "ps2_defines.v"
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module ps2_sim_top
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(
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    wb_clk_i,
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    wb_rst_i,
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    wb_cyc_i,
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    wb_stb_i,
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    wb_we_i,
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    wb_sel_i,
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    wb_adr_i,
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    wb_dat_i,
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    wb_dat_o,
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    wb_ack_o,
70 11 mihad
 
71 2 mihad
    wb_int_o,
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    ps2_kbd_clk_io,
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    ps2_kbd_data_io
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    `ifdef PS2_AUX
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    ,
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    wb_intb_o,
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    ps2_aux_clk_io,
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    ps2_aux_data_io
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    `endif
83 2 mihad
) ;
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input wb_clk_i,
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      wb_rst_i,
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      wb_cyc_i,
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      wb_stb_i,
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      wb_we_i ;
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input [3:0] wb_sel_i ;
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input [2:0]  wb_adr_i ;
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input [31:0] wb_dat_i ;
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output [31:0] wb_dat_o ;
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output wb_ack_o,
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       wb_int_o ;
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101 2 mihad
inout  ps2_kbd_clk_io,
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       ps2_kbd_data_io ;
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`ifdef PS2_AUX
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output wb_intb_o ;
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inout  ps2_aux_clk_io ;
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inout  ps2_aux_data_io ;
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`endif
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wire ps2_kbd_clk_pad_i  = ps2_kbd_clk_io ;
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wire ps2_kbd_data_pad_i = ps2_kbd_data_io ;
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wire ps2_kbd_clk_pad_o,
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     ps2_kbd_data_pad_o,
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     ps2_kbd_clk_pad_oe_o,
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     ps2_kbd_data_pad_oe_o ;
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ps2_top i_ps2_top
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(
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    .wb_clk_i              (wb_clk_i),
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    .wb_rst_i              (wb_rst_i),
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    .wb_cyc_i              (wb_cyc_i),
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    .wb_stb_i              (wb_stb_i),
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    .wb_we_i               (wb_we_i),
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    .wb_sel_i              (wb_sel_i),
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    .wb_adr_i              (wb_adr_i),
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    .wb_dat_i              (wb_dat_i),
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    .wb_dat_o              (wb_dat_o),
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    .wb_ack_o              (wb_ack_o),
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130 2 mihad
    .wb_int_o              (wb_int_o),
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    .ps2_kbd_clk_pad_i     (ps2_kbd_clk_pad_i),
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    .ps2_kbd_data_pad_i    (ps2_kbd_data_pad_i),
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    .ps2_kbd_clk_pad_o     (ps2_kbd_clk_pad_o),
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    .ps2_kbd_data_pad_o    (ps2_kbd_data_pad_o),
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    .ps2_kbd_clk_pad_oe_o  (ps2_kbd_clk_pad_oe_o),
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    .ps2_kbd_data_pad_oe_o (ps2_kbd_data_pad_oe_o)
138 11 mihad
 
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    `ifdef PS2_AUX
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    ,
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    .wb_intb_o (wb_intb_o),
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    .ps2_aux_clk_pad_i (ps2_aux_clk_io),
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    .ps2_aux_data_pad_i (ps2_aux_data_io),
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    .ps2_aux_clk_pad_o (ps2_aux_clk_pad_o),
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    .ps2_aux_data_pad_o (ps2_aux_data_pad_o),
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    .ps2_aux_clk_pad_oe_o (ps2_aux_clk_pad_oe_o),
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    .ps2_aux_data_pad_oe_o (ps2_aux_data_pad_oe_o)
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    `endif
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) ;
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assign ps2_kbd_clk_io  = ps2_kbd_clk_pad_oe_o  ? ps2_kbd_clk_pad_o  : 1'bz ;
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assign ps2_kbd_data_io = ps2_kbd_data_pad_oe_o ? ps2_kbd_data_pad_o : 1'bz ;
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`ifdef PS2_AUX
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assign ps2_aux_clk_io  = ps2_aux_clk_pad_oe_o  ? ps2_aux_clk_pad_o  : 1'bz ;
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assign ps2_aux_data_io = ps2_aux_data_pad_oe_o ? ps2_aux_data_pad_o : 1'bz ;
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`endif
159 2 mihad
endmodule

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